The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> regulator stability
https://designers-guide.org/forum/YaBB.pl?num=1358757633

Message started by james_lanren on Jan 21^st, 2013, 12:40am

Title: regulator stability
Post by james_lanren on Jan 21^st, 2013, 12:40am

I have designed a linear regulator with a two-stage amplifier with an nmos driver. I used miller capacitor and a nulling resistor for compensation at the second stage. I also checked the frequency response and the phase margin are quite good (90 deg and even more) across different load current (max ~1mA). However, when I did a transient sim at a particular load current (200uA), I saw oscillation at the output. It puzzles me becoz the frequency response satisfies the stability criteria at that load current.

Could the miller compensation make the second stage a potential oscillation source? Should I separate it from the first stage and output to check its stability? Any idea to overcome? Thanks

Title: Re: regulator stability
Post by raja.cedt on Jan 21^st, 2013, 1:08am

Hello,
1. You have to check stability at lower current because regulator output pole (~gm2/CL) will be near to UGB or some cases even below. Please check this and post result whenever you want some good answer in short time.
The above statement will be useful only if your second pole is non-dominate.

2.Some time phase margin may not guarantee stability due to non-monotonicity in the bode plot. In that case either you have to use Nyquist plot (tough for an ckt designers) or pole zero analysis on closed loop and last but and best case transient.

Thanks,
Raj.

Title: Re: regulator stability
Post by Aman on Jan 22^nd, 2013, 5:32pm

For a NMOS driver i.e. power device, the O/P impedance is maximum at minimum load current condition. The dominant pole is located at the first stage of amplifier/the non-dominant poles are located at amplifier output and load. You want to test your stability in the zero-load-current condition to simulate the worst-case. This is unlike the case for a PMOS power device, where peak current is the least stable bound.

-Aman

Title: Re: regulator stability
Post by raja.cedt on Jan 23^rd, 2013, 1:33am

hello Aman,
i don't think worst case will be differ for pmos and nmos. Because in case of pmos second pole depends on gds2/CL which is directly depends on current, where as in case of nmos second pole depends on gm2/CL which is also depends on directly on current. Correct me if am wrong.

Thanks,
Raj.

Title: Re: regulator stability
Post by Aman on Jan 31^st, 2013, 5:02pm

Raj,

I guess the answer is a bit tricky and depends on high-frequency PSRR i.e. compensation design. Generally speaking in PMOS driver designs dominant pole is located at the output, which is not the case in NMOS driver type designs. So, for a NMOS driver LDO the dominant pole at error amplifier remains somewhat fixed and the parasitic/secondary pole O/P at low currents move close-in. Thus, if you are coming from a PMOS LDO design, worst-case scenarios might get reversed.

-Aman

Title: Re: regulator stability
Post by Erez_Sarig on Feb 7^th, 2013, 1:10pm

Hi,

If you used Miller with nulling resistor somewhere in the middle of the signal path which means for example between stages you need to check their local loop as well.

Erez