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Design Languages >> Verilog-AMS >> ADC simulation Verilog A
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Message started by batmanbeginz on Feb 1^st, 2013, 11:31pm

Title: ADC simulation Verilog A
Post by batmanbeginz on Feb 1^st, 2013, 11:31pm

Hi all,

I am trying to simulate an ADC [Analog to digital converter] on verilog-A, using MOSFET models generated from TCAD tools.
In order to quantify ADC performance in terms of SNR etc. I need to include noise in my simulations too.
Can someone help to identify where I can include noise sources in the simulation process and how to include them ?

I know that this is very broad question, however as I am a beginner in this field any pointers will be great.
I was thinking of 2 approaches: either include sources of thermal noise etc in TCAD models and somehow use this information in ADC Verilog A simulation,
or simulate ADC in verilog A, using a noise generating function.

Can anyone help to identify pros-cons and more importantly feasibility of these approaches ?

Thanks in Advance !!

Title: Re: ADC simulation Verilog A
Post by sourav on Mar 16^th, 2013, 1:15pm

hi batmanbeginz

what kind of ADC you are trying to simulate?? For my case I am working on delta sigma ADC and i am using the DFT function in the cadence calculator. Forget about the thermal noise, there is other kind of noise present too in the ADC circuits. That is quantization noise and from DFT you can calculate the signal to noise ratio. After getting that quantization noise think about the thermal noise. 8-)

sourav