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Design Languages >> Verilog-AMS >> Library section includes in Verilog-AMS?
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Message started by Chris Atkins on Feb 8^th, 2013, 8:23am

Title: Library section includes in Verilog-AMS?
Post by Chris Atkins on Feb 8^th, 2013, 8:23am

I currently have a spectre dvc_model.scs file that looks like this:

Code:

library mylib

section SLOW
ahdl_include "dvc_model.vams"

endsection SLOW

section NOM
ahdl_include "dvc_model.vams"

endsection TYP

section FAST
ahdl_include "dvc_model.vams"

endsection FAST

endlibrary mylib

I would like to do this purely in Verilog-AMS so that when I use the config view in Virtuoso, it netlists properly.

Is it possible to do this in Verilog-AMS? I can't find anything regarding sections in the manual.

Thanks,

Chris

Title: Re: Library section includes in Verilog-AMS?
Post by Geoffrey_Coram on Feb 11^th, 2013, 12:34pm

Why don't you make Rpoly, Cpoly, etc. parameters of the dvc_ modules, and pass in the appriopriate parameter value in the library section?