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Design >> Mixed-Signal Design >> Noise in SAR ADC
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Message started by SATurn on Feb 10^th, 2013, 6:01am

Title: Noise in SAR ADC
Post by SATurn on Feb 10^th, 2013, 6:01am

Hello,

I was wondering how one could estimate the noise in the cap based dac ? Suppose you have an 8-b SAR ADC which means you need 9 clock cycles to accomplish the conversion. The first one is to sample the input voltage and the rest are for step by step conversion (binary search). So in total, one can count that 9 times the process of sampling or charge sharing will happen.

So now my question is that how the noise of this DAC depends on:

(a) unit cap size
(b) number of cap-based DAC bits or the number of clock cycles for conversion

Thanks,

Armin

Title: Re: Noise in SAR ADC
Post by dcic on Feb 20^th, 2013, 9:08pm

To estimate the noise sampled during the sampling period, one typically regards the DAC as a simple lump cap in series with a sampling switch. In you case, it will be whatever the size of cap that sufficiently minimize thermal noise for the 8bit ADC, given the full-scale input. Once the sampling is done, DAC switching during conversion does not contribute to further thermal noise increasing.
Number of conversion cycles will depend on whether redundancy is implemented; if not, 8bit SAR takes 1cycle of sample + 8 cycles of conversion.

Title: Re: Noise in SAR ADC
Post by Vladislav D on Feb 23^rd, 2013, 2:45am

dcic wrote on Feb 20^th, 2013, 9:08pm:

Once the sampling is done, DAC switching during conversion does not contribute to further thermal noise increasing.

Not correct. Switching elements in the DAC introduce noise. Voltage switches in a charge redistribution DAC have finite ON-resistance, which essentially generates thermal noise.

dcic wrote on Feb 20^th, 2013, 9:08pm:

Number of conversion cycles will depend on whether redundancy is implemented; if not, 8bit SAR takes 1cycle of sample + 8 cycles of conversion.

There are many possibilities here. It depends.