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Design >> RF Design >> PA design: O/P parasitic capacitance(pad+bondwire+pcb)
https://designers-guide.org/forum/YaBB.pl?num=1360741516

Message started by mixed_signal on Feb 12^th, 2013, 11:45pm

Title: PA design: O/P parasitic capacitance(pad+bondwire+pcb)
Post by mixed_signal on Feb 12^th, 2013, 11:45pm

Hi,
I am designing a PA as shown in schematic. Some specs are:
2.4 GHz
ultra low power (<1mA)
moderate linearity (modulation is QPSK, moderate PAR, either class A or class AB)

The problem is my gain falls by 2dB (w.r.t mid band gain) at 2.4GHz when O/P is loaded with 200f parasitic capacitance. The O/P shall drive offchip matching network and then 50 ohm. I have the following questions:

1. How do I get fair estimate of parasitic cap Cpar (bond pad+bond wire+ package pad+ pcb)
2. Is it possible to tune the parasitic cap out by including it in the cap (C) of matching network.
3. If yes then onchip or offchip cap for matching solves it best? The matching network upconverts 50 ohm to 500 ohm.

Title: Re: PA design: O/P parasitic capacitance(pad+bondwire+pcb)
Post by Maks on Feb 17^th, 2013, 1:28am

mixed_signal wrote on Feb 12^th, 2013, 11:45pm:

1. How do I get fair estimate of parasitic cap Cpar (bond pad+bond wire+ package pad+ pcb)

I can try to answer the first question.
You can get an accurate estimate of the on-chip parasitic capacitance using parasitic extraction software (StarRC, QRC, Calibre XRC, F3D,...). The on-chip parasitic capacitance is caused both by pad capacitance, and by interconnects capacitance (in your case, source/drain interconnects capacitance, and maybe source/gate and drain/gate).

For the off-chip capacitance, you can probably use some package and PCB simulation software, but its use requires some expertise. You can probably do some hand estimations of the wirebond and PCB capacitance.

Max
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Title: Re: PA design: O/P parasitic capacitance(pad+bondwire+pcb)
Post by mixed_signal on Feb 17^th, 2013, 12:02pm

Thanks Max!