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Design Languages >> Verilog-AMS >> wires to vec in VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1360850996

Message started by jmith on Feb 14^th, 2013, 6:09am

Title: wires to vec in VerilogA
Post by jmith on Feb 14^th, 2013, 6:09am

Im trying to make a wires to vector converter module in VerilogA. Is this correct?

Code:

module wires_to_vec(a, b, q);
input a, b;
output [0:1] q;
electrical a, b;
electrical [0:1] q;

analog
begin
V(q[0]) <+ V(a);
V(q[1]) <+ V(b);
end

endmodule

Title: Re: wires to vec in VerilogA
Post by boe on Feb 15^th, 2013, 6:09am

Jmith,
your code is equivalent to voltage-controlled voltage sources at q[0:1].
Is that what you want?

- B O E