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Design >> RF Design >> Resonance load or (inter-stage) impedance matching for CMOS amplifiers
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Message started by vivarf on Feb 17^th, 2013, 5:52pm

Title: Resonance load or (inter-stage) impedance matching for CMOS amplifiers
Post by vivarf on Feb 17^th, 2013, 5:52pm

Hi all,

Given a millimeter-wave multi-stage common source/cascode CMOS amplifier. Which method would be the proper design: inter-stage conjugate matching or resonance load (adjacent stage should be place close in the layout)?

For CMOS transistor, it is gate-source voltage controlled device, it is more important to provide high voltage (not power) to the gate. So if the adjacent stage is placed very close: resonance load is the proper way, thus complex inter-stage matching is relaxed, chip size is saved. However, in most of state of the arts literature I have reviewed, inter-state conjugate matching is often chosen. Why go through to much trouble with inter-stage matching design but simply resonance LC circuit?

Could anyone provide some idea? Thanks in advance.

Title: Re: Resonance load or (inter-stage) impedance matching for CMOS amplifiers
Post by aaron_do on Feb 17^th, 2013, 9:58pm

Hi,

treating the MOSFET's input as purely capacitive is only really adequate at low frequencies. At millimeter-wave frequencies, you need to keep in mind the gate resistance. If you treat the gate resistance and capacitance as being in series, then the maximum power to the gate resistance also results in the maximum voltage across the gate capacitance. Its a simplified model though. As gain is scarce at millimeter-wave frequencies, it may be better to do an actual impedance match since in theory you can get higher gain.

It also depends on the Q of the inductors and capacitors which you have to do the matching. For the specific kind of matching network you want to use, the network Q and the component Q, you may or may not see any benefit.

Last point is that even if you were to treat the input impedance as purely imaginary, the highest voltage gain is not achieved with an LC resonance. You can always get higher gain by using a step-up transformer. The tradeoff is typically bandwidth and whether or not its practical to implement.

regards,
Aaron

Title: Re: Resonance load or (inter-stage) impedance matching for CMOS amplifiers
Post by vivarf on Feb 18^th, 2013, 2:52am

Thanks aaron,

What you said about MOSFET is true. And if the first stage is treated as voltage source then definitely conjugate matching will provide maximum voltage drop at the next gate. However, I believe that the first stage is more like current source. You may want to maximize the current go through the gate of the second stage which leading to using resonance LC at the output of the first stage. Am I missing something???

Title: Re: Resonance load or (inter-stage) impedance matching for CMOS amplifiers
Post by vivarf on Feb 18^th, 2013, 6:36pm

vivarf wrote on Feb 18^th, 2013, 2:52am:

I think I was confused :-[. Just made a calculation, eventually, matching network provides the largest voltage on Cgs :).