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Design Languages >> Verilog-AMS >> need solution for following error in rtl synthesis tool in cadence
https://designers-guide.org/forum/YaBB.pl?num=1362563389

Message started by aathi27 on Mar 6^th, 2013, 1:49am

Title: need solution for following error in rtl synthesis tool in cadence
Post by aathi27 on Mar 6^th, 2013, 1:49am

reg [7:0]cb[3:0][3:0];
|
Error : Verilog-2001 feature. [VLOGPT-3] [read_hdl]
: Multiple dimensions in file './sad.v' on line 8, column 22.
: The design must be read in with 'read_hdl -v2001'.

Title: Re: need solution for following error in rtl synthesis tool in cadence
Post by Geoffrey_Coram on Mar 6^th, 2013, 5:17am

Did you read the error message? It says you have to specify -v2001 because you're using a feature that is from a later version of the language than your simulator supports by default.