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Design >> Analog Design >> To increase the unity gain bandwidth of one rail-to-rail output amplifier
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Message started by ywguo on Mar 10^th, 2013, 7:43am

Title: To increase the unity gain bandwidth of one rail-to-rail output amplifier
Post by ywguo on Mar 10^th, 2013, 7:43am

Hi Guys,

I have a PMOS input rail-to-rail output amplifier, which has around 500MHz ~ 600 MHz unity gain frequency. What can I do to increase he unity gain bandwidth without sacrifice too much voltage headroom of the output stage.

The load is a 1pF cap and 4kΩ resistor in parallel. Any comments are appreciated.

Best Regards,
Yawei

Title: Re: To increase the unity gain bandwidth of one rail-to-rail output amplifier
Post by Vladislav D on Mar 10^th, 2013, 9:10am

Hi,
Headroom has nothing to do with bandwidth! Looks like you don't understand fundamental trade-off in amplifiers design. I would recommend to read some basic books. For example, "Analog Design Essential" by W. Sansen.

If the amplifier designed properly (questionable? maybe), unity-gain-bandwidth product is defined by the compensation capacitor and and the tail current of the differential pair. So, increasing tail current or decreasing compensation capacitor improves UGBWP. To keep the same PM you have to increase the quiescent current of the output stage. I assume, you cannot decrease a load cap. Therefore, increasing BW leads to a larger current consumption.

Of course, my description is too optimistic since you have already a very high bandwidth. Various small parasitic poles at different nods can affect frequency response of an amplifier. So, more design efforts will be needed.

Title: Re: To increase the unity gain bandwidth of one rail-to-rail output amplifier
Post by raja.cedt on Mar 10^th, 2013, 2:06pm

Hello ywugo,
as vladislav pointed out you can refer a good book or Design procedures for a fully differential folded-cascode CMOS operational amplifier.
Here are the few Common guidelines.
1.A well compensated Amplifier UGB will be gm/Cc, so roughly estimate these values
2. Place other non dominate poles >2*UGB, like output pole gm2/Cl and one more pole very specific to folded cascode at the current summation node (gm39/cap).
3. If you want to adjust slightly this design without doing from starting, increase tail current and as well as cascode stack or output stage current, whichever pole dominate's.
4.Adjust output pole by increasing current and device size, so as not to compromise on output swing.

Thanks,
Raj.

Title: Re: To increase the unity gain bandwidth of one rail-to-rail output amplifier
Post by Kevin Aylward on Jul 6^th, 2013, 7:22am

Replace current sources M20 and M21 with resistors and setup the cascode bias accordingly with mirrored a device and resistor. This will greatly reduce the capacitance on their nodes, at the expense of DC gain, possibly. Increase the lengths of most devices and eliminate their m multipliers. This will reduce their parasitics. Regarding headroom and bandwidth. Yes they do interact. If a reduced output voltage swing could be tolerated, then a push/pull source follower could be added, with the 2nd gain stage then greatly reduced in size, reducing its capacitance loading. The modified topology might well allow for higher bandwidth. Do you actually need a class B output?