The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Single line assignment to multiple variable
https://designers-guide.org/forum/YaBB.pl?num=1363693096

Message started by Tobben24 on Mar 19^th, 2013, 4:38am

Title: Single line assignment to multiple variable
Post by Tobben24 on Mar 19^th, 2013, 4:38am

Hi,

Is it possible to do single line assignment to multiple variables? Something like this:

real one,two,three;
one,two,three = 0;

Title: Re: Single line assignment to multiple variable
Post by Geoffrey_Coram on Mar 20^th, 2013, 6:24am

I don't believe the syntax allows
one,two,three = 0;

I believe the lastest (digital) Verilog supports initialization as part of the declaration:
real one=0,two=0,three=0;

and I've found some simulators support new digital features in the AMS context.

Of course, if you just want to do it on one line, you could do
one=0; two=0; three=0;
The statements don't have to be on separate lines.

Title: Re: Single line assignment to multiple variable
Post by Tobben24 on Mar 20^th, 2013, 7:09am

Okay, thanks for the reply:)

Title: Re: Single line assignment to multiple variable
Post by Paul Floyd on Mar 20^th, 2013, 9:44am

Tobben24 wrote on Mar 19^th, 2013, 4:38am:

Hi,

Is it possible to do single line assignment to multiple variables? Something like this:

real one,two,three;
one,two,three = 0;

Variables should be default initialized to zero, so in this case your assignment does nothing. If you want a different value, that's another matter.

If it were allowed, I'd want to follow C++ syntax, where it would be

a = b = c = 0;

A+
Paul