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Simulators >> Circuit Simulators >> problem with gated current source
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Message started by sourav on Mar 21^st, 2013, 1:47am

Title: problem with gated current source
Post by sourav on Mar 21^st, 2013, 1:47am

Hi,

i want to design a gated current source. Here i have used a simple current mirror topology. Current through PM12 and PM13 will be controlled through the signal phi1 and phi2. Before adding these switches i was getting current 128 times of 40nA as I fixed the W/L ratio 128 times of PM10 and PM11.
After adding the switches i was expecting current only during the on time of phi2 and zero value when it is off. I have taken here ideal switches and they are implemented in Verilog A with on resistance of 1ohm and Off resistance of 100Mohm.
i am using gpdk 180nm technology file in cadence. after the simulation i am getting an unstable current instead of constant current. i have observed several times that whenever i am using some clock in mos circuits it generates some random fluctuation in current at the other terminals.

please tell me the reason behind it and give me some suggestion

thanks

Title: Re: problem with gated current source
Post by Geoffrey_Coram on Mar 25^th, 2013, 7:37am

It's tricky to write a good switch model in Verilog-A.

Did you try using a built-in switch provided by your simulator?

Title: Re: problem with gated current source
Post by Kevin Aylward on Jul 7^th, 2013, 3:52am

Without even examining anything about your circuit, but based on the graphs only, I would first suggest that you set the simulator to do “Gear only” for these runs.