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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Converting integer to string in Verilog-A https://designers-guide.org/forum/YaBB.pl?num=1363944310 Message started by Deyan Levski on Mar 22nd, 2013, 2:25am |
Title: Converting integer to string in Verilog-A Post by Deyan Levski on Mar 22nd, 2013, 2:25am Hello everyone, I am trying to create a "filewriter" block in Verilog-A which automatically generates a new file on every simulation run, for the purpose of some Monte Carlo simulations. I can use the $random function, to generate a random integer, to be used for the unique file name for every run. However I can not figure out how to convert integer to string in Verilog-A. To illustrate, here is an excerpt of what I am trying to do: parameter real vThreshold = 1.65 ; //parameter string fileName = "fileName.txt"; parameter string filePath = "/tmp/"; string concat_var; integer outputFileId; string fcat; analog begin @(initial_step) begin fcat = $random; // Apparently this is not allowed, how do I convert $random to string??? concat_var = {filePath,fcat}; // Concatinate path and unique file name outputFileId = $fopen(concat_var); // Open a file in the specified path with the random name end @ (cross(V(CLK) - vThreshold, 1)) // On rising edge of clock begin appending to file begin $fwrite(outputFileId, "%1.24f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f\n", $realtime, V(vIn[15]),V(vIn[14]),V(vIn[13]),V(vIn[12]),V(vIn[11]),V(vIn[10]),V(vIn[9]),V(vIn[8]),V(vIn[7]),V(vIn[6]),V(vIn[5]),V(vIn[4]),V(vIn[3]),V(vIn[2]),V(vIn[1]),V(vIn[0]) ); $fflush(outputFileId); end end It might be extremely simple and embarrasing asking such questions, but I was not able to find a solution over the net, nor the designer's guide manual to Verilog-A. Regards, Deyan |
Title: Re: Converting integer to string in Verilog-A Post by Geoffrey_Coram on Mar 22nd, 2013, 7:25am Is Code:
SV 1800-2009, section 6.16.15: str.realtoa(r) stores the ASCII real representation of r into str (inverse of atoreal). |
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