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https://designers-guide.org/forum/YaBB.pl Design Languages >> VHDL-AMS >> Architecture name through hierarchy https://designers-guide.org/forum/YaBB.pl?num=1364573171 Message started by Basil1402 on Mar 29th, 2013, 9:06am |
Title: Architecture name through hierarchy Post by Basil1402 on Mar 29th, 2013, 9:06am Hello all. I'm having trouble with my implementation. Here is what I am trying to do : - I have a testbench file, in which I instanciate a top module. - In this top module, I instanciate a couple of smaller modules, including one containing many different architectures. I want to chose the implemented architecture thanks to an argument specified in the testbench file. What I tried : - in the testbench file, declaring a string matching one of the architecture and sending it to the top module as a generic. - in the top module, I created a generic string (say arch_name) and used it to instanciate my smaller module. With some extremely simplified code : -- test bench -- [...] ARCHTECTURE beh OF tb_top is [...] system : ENTITY top(beh) GENERIC MAP("arch_name") -- arch_name is a real architecture name of module [...] -- top -- ENTITY top IS GENERIC(example : string) [...] ARCHITECTURE beh OF top IS [...] module_1 : ENTITY module(example) [...] The "vacom" command works fine, but when I try "vasim", it cannot build my system, and Questa tells me that the architectureexample of module does not exist. And it is correct : it is the architecture arch_name I want to use. But it seems it cannot go all the way through the hierarchy. Do you know : 1- if it is doable ? 2- what the syntax is ? Thank you in advance. Basil1402 |
Title: Re: Architecture name through hierarchy Post by jerome_ams on Aug 20th, 2013, 7:29am Hi, The usual way to deal with such a thing is to use configuration files. In such a file you declare the particular architecture you want to bind for your particular setup. Hope it helps Cheers Jerome |
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