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Simulators >> RF Simulators >> DC simulation setup for LNA in Cadence
https://designers-guide.org/forum/YaBB.pl?num=1365015952

Message started by sweetchoto on Apr 3^rd, 2013, 12:05pm

Title: DC simulation setup for LNA in Cadence
Post by sweetchoto on Apr 3^rd, 2013, 12:05pm

Dear All,

I am a new user to Cadence and have to use it for designing a LNA. I was wondering if some one can provide/point me a tutorial with step by step information of how to setup DC simulation in order to determine suitable bias point for my transistor.

Thanks,
Sweetchoto

Title: Re: DC simulation setup for LNA in Cadence
Post by sheldon on Apr 3^rd, 2013, 9:47pm

This might be helpful

http://www.cadence.com/Community/blogs/rf/archive/2011/08/11/measuring-fmax-for-mos-transistors.aspx?postID=1292802