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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Design of a 40 MHz pierce oscillator(quartz), steps to follow https://designers-guide.org/forum/YaBB.pl?num=1365066477 Message started by Pictou on Apr 4th, 2013, 2:07am |
Title: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 4th, 2013, 2:07am Hello everyone, I'm trying to design a 40 MHz Pierce Oscillator. Even if my circuit works (sometimes) I can't justify why as my simulations are not validating the Barkhausen criteria. What I would like to know is the steps to follow to design this oscillator. I will try to be succint. First, my schematic, I made a simplified schematic, I will deal with corner analysis later. Is this schematic good to you? (I uploaded it in a pdf so it won't be ugly) http://www.pdfhost.net/index.php?Action=Download&File=8b98e6df4f5fd6a4c3a21088dceef4b0 It's basically, an inverter amplifier (common source NMOS), a buffer to "transfer the gain" to the Xtal and the Xtal is connected to the input of the amplifier. My first goal is to match the Barkhausen criteria. Phase shift after a loop is +/- n*360°. Gain when oscillation is stable should be equal to 1. My question is simple, what steps should I follow to design a circuit that will match the Barkhausen criteria? I tried a lot of things, nothing worked. Here I'm going to talk about my next attempt and I hope you will be able to guide me. The approach I am going to use is the Negative Resistance. This approach focuses on two main points : The value of the negative resistance must be higher than the Equivalent Serie Resistance of the crystal and the transconductance must match a certain value. The value of the transconductance is given by a relation that I calculated. Knowing the transconductance I'm able to determine the current and the Overdrive voltage of the transistor acting as an amplifier. So I have my geometry for my transistors. With this approach I can know if I will have enough gain to start the oscillation. My problem is the phase. In all examples that I saw, the amplifier was used in its bandwidth, so the phase shift provoked by the amplifier was -180° (or 180°) like in theory, my problem is that at 40 MHz I'm more close to -220° than 180°, how can I fix that? Is it even a problem? I'm trying to design an oscillator, but I don't even know how to validate it, if you can help me, I would really appreciate. Thank you very much. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by raja.cedt on Apr 5th, 2013, 10:35am Dear Pictou, yes in theory it can oscillate but why don't you follow some traditional crystal oscillator design like colpitts or some other std VCO?i didn't understand "what steps should I follow to design a circuit that will match the Barkhausen criteria". Up to my knowledge make sure that you have >1 gain at 40Mhz and enough phase, try to check through AC sim. What do you mean by the amplifier was used in its bandwidth. Normally amplifier will contribute some phase in excess to it's dc phase, for example take 3 stage ring vco in addition to 180 deg phase each contribute 60deg at the oscillation frequency. I guess in your case amplifier is providing 40deg in-excess and rest of the 120 deg by Cristal tank at the frequency of oscillation. What do you want to validate, to make sure it is oscillating normal transient analysis or PSS will be sufficient. If you want check noise performance use P-noise. Thanks, Raj. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 5th, 2013, 11:40am Dear Pictou, Your basic statements "My first goal is to match the Barkhausen criteria" and "The value of the negative resistance must be higher than the Equivalent Serie Resistance of the crystal and the transconductance must match a certain value.", I think need some additional thought. First, the Barkausen criteria is not a condition that guarantees steady-state oscillation. For details, you might examine the URL: http://web.mit.edu/klund/www/weblatex/node4.html Second, in a negative resistance simulation, the fact that the magnitude of the negative resistance (and assuming the real impedance is negative in sign) exceeds the series resistance of the quartz crystal unit indicates that the transconductance exceeds the minimum required value for positive gain. > My problem is the phase. If you use the result of from your impedance analysis of the ports the crystal unit are attached, you may then compute the input phase of the oscillating amplifier. You have already computed the real part. Typically, the reactive portion for a quartz crystal oscillator amplifier will be capacitive. For steady-state oscillation, the condition is: Re{ Zin } + Re {Xtal_unit} = 0 and Im{ Zin } + Im{ Xtal_unit} = 0 From a large signal negative resistance simulation, you can determine the amplitude at which the amplfier will limit to produce the proper real impedance to balance that of the quartz crystal unit. At that same amplitude, you can determine the impedance of the sustaining amplifier and hence from the second equation determine the frequency of oscillation. This assumes there are no other dominant sources of oscillation (i.e., overtones or parasitic modes). There are many texts on quartz oscillator design - and they are rich with information since the basic circuit was created in the late 1800's and early 1900's. I would suggest you consider studying some of them to get a good understanding of these circuits. They appear simple, but are deceptively so! Texts by Ballato, Rhea, and Parzen come to mind. Tutorials by John Vig are also a very good introduction to the field. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by wave on Apr 5th, 2013, 12:08pm Your schematic is peculiar in a few ways. I've never seen a pierce oscillator with so many biases and even two stages! An oscillator generally is large signal, so you'll be swamping out the biases of the extra transistors. Start with a simple inverting stage. You talk about Loop Gain (Barkhausen), but your schematic neither shows a Feedback Resistor, nor a model of the crystal. Without either, you won't be able to simulate Loop gain or phase. You would be able to simulate Neg R, and I encourage you to do so. However, that is small signal, and you will be dealing with a larger signal in reality. Good Luck, WAVE ;D |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 5th, 2013, 12:16pm Hi Wave, Negative resistance analysis can be a large or small signal simulation. For a quick estimate of start-up gain over PVT, a small signal simulation may be performed. However, to assess limiting and the actual frequency of oscillation, a large signal negative resistance analysis (transient) is required. Also, a parallel resistor (which I assume you are referring to) is only required if the DC condition does not force the amplifier into its high gain region. In a Pierce design formed by an inverter as the sustaining amplifier, the use of a parallel resistor is required. I am not sure of Pictou's biasing conditions and hence am not sure a parallel resistor is required. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by wave on Apr 5th, 2013, 2:00pm SMLogan - NegR is basically an AC simulation. Related to Gm*Rout. Small signal. Transient is completely different analysis. I agree it should also be performed, for large signal behavior. There is a direct correlation of startup results with Neg R and Transient, but don't combine or confuse the two. In fact, there simulation test benches are necessarily different. Sounds like we are both confused with his biasing. Yes, the traditional large R is for biasing. Plus, there can be significant interplay between it's size and other parasitic elements, that affect NegR and startup! That is not obvious nor documented many places. Wave |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 5th, 2013, 2:25pm Hi Wave, Thank you for your comments! To be honest - and I am only trying to help - there is an analogous large signal transient negative resistance simulation. It was actually the subject of my thesis. It is quite useful in examining the limiting mechanism of a sustaining amplifier and determining an accurate prediction of the oscillation frequency. I have used it for years. I hope you will not take my comments the wrong way! I agree, also, with your comments concerning the feedback resistor. I think we are both consistent in that respect! Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 8th, 2013, 1:28am Hello everyone and thank you very much for your answers! ------------------------------------------------------------------- @raja.cedt I'm trying to design a Pierce oscillator, however in all the schematic I found, the schematic wasn't transistor level. I didn't use a regular inverter because I couldn't control the output voltage levels. I have several constraints about my input voltage level and ouput voltage level. I must use 5V supply voltage on transistors that can hold only 3.3V and my output level must be 1.2V. (However you couldn't know that, I forgot to mention it, I'm sorry). About the Barkhausen criteria, actually my testbench was wrong so I thought that I didn't match the Barkhausen criteria, but now with proper simulation configuration I'm following the criteria. I've been on this design for a month now. From all the publications and books I read, the amplifier inverter was always shifting the phase by 180° (therefore the inverter amplifier was in its bandwidth). I was so doubtful about my work that I started to question everything in my design. My superior told me that the design oscillator should take something like 2 weeks, and I'm stuck on it for 1 month already so I was quite panicked. Yes the Pnoise is my next step, I mean... as soon as my oscillator works fine and I know why. --------------------------------------------------------------- @smlogan, thank you for helping me again http://web.mit.edu/klund/www/weblatex/node4.html okay, my world if falling apart... Well I prefer negative resistance anyway. Quote:
Thank you very much I tried to find the meaning of the negative resistance for a while, thanks to you I finally have it. I'll try to get these texts and tutorials, so I can fully understand what I'm doing. --------------------------------------------------------------------- @wave Yes you are right, I removed the follower stage (as I didn't need to adapt the impedance anyway). I couldn't use an inverter amplifier because I have to control the output voltage levels. I had to use the numerous bias, because of another issue. I'm using 5V supply voltage on 3.3V transistors, I have to "lower" the voltage on some transistors so they won't be overstressed (but I haven't taken care of this problem yet). And I'm sorry I forgot to draw the parallel resistance but it's present. My new schematic : http://www.pdfhost.net/index.php?Action=Download&File=14f34384d8c3b7aac18e8950f4d4a05f -------------------------------------------------------------------------- Thank you all again for your help. My simulations are now working, I'm oscillating, PSS does converge (but I will have to increase the accuracy). However I have another problem. The drive level of the crystal model is only 100uW and I'm consuming up to 1069uW. I saw in a publication that to solve this, you need to add a resistor between the amplifier output and the crystal input. Will this addition change all my previous calculations? Thank you again. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 9th, 2013, 12:40pm Hi Pictou, However I have another problem. The drive level of the crystal model is only 100uW and I'm consuming up to 1069uW. I saw in a publication that to solve this, you need to add a resistor between the amplifier output and the crystal input. Will this addition change all my previous calculations? The use of a series resistor is not an efficient means of reducing power dissipation in a quartz crystal unit. I would suggest you consider the major factors influencing quartz crystal unit power dissipation outlined in the following: http://www.electronicproducts.com/Passive_Components/Oscillators_Crystals_Saw_Filters/Power_dissipation_of_bulkwave_quartz_xtal_units.aspx Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 10th, 2013, 2:18am Hello logan, Very interesting article, there were a lot of information I haven't seen in any other article. So if I understand correctly, the way presented to lower the power dissipation in the crystal is to change the load capacitance that the crystal sees. This way we shift the oscillation frequency a little in order to avoid the peak power consumption. I tried this method but I had other issues, such as : With the load capacitance specified by the crystal manufacturer (14pF) I have a swing of 2.5V for an oscillation frequency of 40.03056 MHz. With 7pF, my swing is now 3.6V and at 40.0326 MHz. However it seems that you didn't have this problem as in your table, the tab nammed limiting voltage remains the same. I think that my oscillator is too basic to use your technique as the power reduction is lowered because I have no voltage control on my output. With 7pF load capacitance instead of 14pF, I went from a power consumption of 1069uW to 866uW. I used the same relation used when we are in resonnance as the phase shift is not that big, I think it's "okay" for a first estimation of the power consumption change. So it's definitely a reduction! But it's not enough. Do you know how to reduce the amplitude of the oscillation? Second issue is that I would like to lower my power dissipation by a factor 10 (going from 1069uW to 90uW), do you think that it's possible with changing the values of the load capacitor? Thank you. EDIT : Power dissipated is not 1069uW but 1455uW... it's even worse than I thought. EDIT 2 : being stuck on your method, I tried to add a resistor, but I really don't know how it is supposed to lower the drive level... |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 10th, 2013, 9:00am Hi Pictou, So if I understand correctly, the way presented to lower the power dissipation in the crystal is to change the load capacitance that the crystal sees. This way we shift the oscillation frequency a little in order to avoid the peak power consumption. Changing the load capacitance has a profound impact on quartz crystal unit power dissipation. However, changing its load capacitance need not impact the frequency of the osicllator as quartz crystal unit manufacturers sell the same quartz crystal unit at different load capacitances. Common values include 20 pf, 14 pf, 7 pf. Many other values are available too. One specifies the recommended load capacitance when one orders the crystal unit. Hence, using a 7 pf load capacitance will not result in a frequency shift if you specify a 7 pf load capacitance for the crystal unit. With the load capacitance specified by the crystal manufacturer (14pF) I have a swing of 2.5V for an oscillation frequency of 40.03056 MHz. With 7pF, my swing is now 3.6V and at 40.0326 MHz. However it seems that you didn't have this problem as in your table, the tab nammed limiting voltage remains the same. I think that my oscillator is too basic to use your technique as the power reduction is lowered because I have no voltage control on my output. With 7pF load capacitance instead of 14pF, I went from a power consumption of 1069uW to 866uW. I used the same relation used when we are in resonnance as the phase shift is not that big, I think it's "okay" for a first estimation of the power consumption change. So it's definitely a reduction! But it's not enough. Do you know how to reduce the amplitude of the oscillation? I am concerned with the method you are using to compute the power dissipation of the quartz crystal unit. I think it may not be correct. For an rms value of limiting voltage of 1.272 Vrms (3.6V/2)/1.414, a load capacitance of 7 pf, an AT cut quartz crystal unit at 40 MHz with a C0 of 3 pf and a series resistance of 20 ohms, I compute a power dissipation of 203.8 uW operating at 600 ppm from series resonance. Most well designed quartz crystal oscillators have some voltage limiting mechanism (other than the supply voltage). There are a number of reasons for this. However, a voltage limiter will reduce your peak-to-peak voltage across the quartz crystal unit. I would suggest double checking the methodology you are using to compute power dissipation. The link I sent you outlines the methodology. I would also possibly suggest examining your oscillator design to study the impact of using a limiting mechanism. Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 10th, 2013, 9:17am Hello, Yeah I forgot that I could ask the manufacturer to give me another load capacitance... forgot again.... Hmm, the method I'm using is the following : (And yes, I just realized that I forgot to put RMS value instead of max) P = R1 * I² = R1 * (V * 2pi * f * C2)². My mistakes were that my Voltage was wrong, I forgot to get the RMS value and I took the swing instead of the amplitude. And I took C2 instead of C0. For "V"oltage I understand my mistake, but are you sure that I must use C0 and not C2? I'll check my math and the methodoly, thank you very much for your help! |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 10th, 2013, 9:29am Hi Pictou, P = R1 * I² = R1 * (V * 2pi * f * C2)². This formula does not provide an accurate measure of quartz power dissipation. This is one of the reasons I created the workbook and sent you the article. Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 11th, 2013, 12:05am Weird, In your article it says P = V²/R. I just assumed that the frequency parameter in the rest of the relation in the article was almost equal to 1 as I'm not really far from serie resonance, is it wrong? I'll use the full relation. EDIT : I'm just wondering something, to use this relation my signal needs to be a sinus right? The shape of my signal is really bad : http://www.hostingpics.net/viewer.php?id=859141oscillatorsaturation.png In order to calculate the power dissipation, I think I need to make my signal a sinus first, what do you think? EDIT 2 : I tried reducing the ampitude of the output oscillations, my first thought was to reduce the gain and increase the load capacitance. It did decrease the oscillation but my DC gets lower and is too close to the ground. I'm still saturating on the bottom curve of the sinus. Do know a way to control the oscillations? |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 12th, 2013, 4:34am EDIT 3 : I couldn't find the result you found. My model is the following : R1 = 21.58 Ohm L1 = 5.15 mH C1 = 3.07 fF C0 = 5 pF The power I'm computing is not good because the frequency I'm oscillating right now is 40.02933 MHz and the serie resonant frequency is 40.02647, so when I'm doing 1-(w/w0)², it's negative, so the power I'm getting is negative, is that correct? What am I doing wrong? |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 12th, 2013, 11:37am Hi Pictou, The oscillation frequency will always be greater than the series resonant frequency for a Pierce oscillator. It appears you may be using a formula in error. Please do not rely on formulas. It is far better to think about what you are trying to compute and derive the necessary equations. Please also make sure you include the input impedance of your sustaining amplifier. The impedance of a quartz crystal unit is a very sensitive function to phase. Hence, its power dissipation is very sensitive to phase. You must include the input reactance of your amplifier to determine the operating point on the quartz crystal unit's impedance characteristic. Hence using the formulas you have written so far are not accurate. Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 15th, 2013, 2:01am Hello Logan, So my oscillator model is here : http://www.pdfhost.net/index.php?Action=Download&File=3b8d65b711906580170bda967684ab48 C1 will include input capacitance of the amplifier. C2 will include output capacitance of the amplifier. Rin will be assumed to be infinite or at least really high Rout is around 83Ohm but it may change. My transconductance is 12mS, so the Rout must be around 83 Ohm to have a gain equals to 1. To determine the drive level of the crystal I'm going to do the following : - To simplify the problem I will assume that the voltage exciting the crystal is perfectly sinusoidal (I know it's not really the case, in my simulation I have a component in the 2nd and 3rd harmonic at about 5% of my fundamental) - I will calculate the impedance of the crystal depending on the pulsation w, the relation can be found here, in the electrical model tab : http://en.wikipedia.org/wiki/Crystal_oscillator I will simulate the circuit to find the oscillation frequency. From this I will compute P = V²/Z(f). Is this method correct? Thank you for your help. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 15th, 2013, 2:49pm Hi Pictou, You are not including the non-linearity of your sustaining amplifier. Hence, the small-signal input impedance of the model will not provide an accurate assessment of the oscillation frequency. As a result, since the operating point is in error, the power dissipation will be in error. I, once again, refer you to the wealth of literature on quartz crystal oscillator design. As I mentioned before, a large signal negative resistance analysis will provide an accurate assessment of sustaining amplifier input impedance from which an excellent estimate of the actual oscillation frequency may be obtained. With respect to your concern on harmonic distortion, the current through the quartz resonator will have very little harmonic distortion. This is why the computation I refer to in the article uses the rms value of the limiting voltage to assess power dissipation. Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 16th, 2013, 12:10am Quote:
If I'm not wrong you are refering to : Quote:
Well I read a lot of things about negative resistance on the internet (publications mostly) most of them stops at the gm_opt to have the best start-up time. I must admit that as most of them stopped their analysis with this tool at this point, I thought that there was nothing more. About quartz litterature, you must be refering to : Quote:
I think I found John Vig tutorial online (is it a powerpoint?). If I wanted to fully understand the negative resistance approach for crystal oscillator, which book should I buy to do so? Thank you for your help and sorry about asking the same questions over and over again, I think that it's still not clear for me. EDIT : Have you got the titles of the books you advised me to read? I tried finding them online and one of them cost like 700 USD I hope it's not that one. EDIT 2 : I think I found them all, but they cost a lot of money as an intern I'm not sure I can afford it. The only book I can buy is : Design of Crystal and other harmonic Oscillators by Benjamin Parzen. Will this book tell me enough about negative resistance? ------------------------------------------------------------------------------ EDIT 3 : Okay, I redid the negative resistance simulation by removing the quartz, adding a current source and the C0 of the quartz I'm using (5pF). Small signal analysis : The AC signal allowed me go get Re(amp) = -147 Ohm. The ESR of the quartz is 21.58 Ohm, therefore I have gain. I got the X(amp) by plotting the imaginary part of the voltage drop across the quartz unit, X(amp) = -287 (Ohm?) The phase calculated is Arctan(-287/-147) = 62.9°. Cadence told me that the phase was -117°, 62.9° - 180° = -117° so it's okay. Now in order to determine the Re(amp) at steady state I need to run a large signal analysis. And the problem is here, how do I do that? Do I put the crystal back? Because if I don't, I don't think that the PSS analysis will converge at all. So my question is how do I simulate large signal analysis? Thank you very much for your help. |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by smlogan on Apr 16th, 2013, 9:59am Hi Pictou, This will be my last post on this topic. You must use large signal analysis to perform your analysis to determine the reactance of the sustaining amplifier to obtain its impedance for use in estimating the operating point on the quartz crystal unit resonance curve. As I have mentioned several times, a small signal analysis will not include limiting effects. Use the Parzen reference for guidance on a negative resistance analysis. There are some errors in his text, but the concept is presented. You may also refer to Section 2 of the following personal document. http://pastelink.me/getfile.php?key=7b1bd3 Shawn |
Title: Re: Design of a 40 MHz pierce oscillator(quartz), steps to follow Post by Pictou on Apr 16th, 2013, 11:54pm I just want to thank you for your help, there is not much on the internet about how to fully and properly design a crystal oscillator and I was very lucky "to meet" you EDIT : Quote:
I understand that, it's just that I have no idea how to do a large signal analysis of the negative resistance. I use a transient analysis on one pin of the current source, from the transient analysis I have a straight line of voltage. From what you said this voltage level should give me information on Re(Zin) and Re(Xtal). Well, I extracted the real part of that signal using the "real" function in cadence, all I have is the exact same voltage level, therefore the imaginary part is 0, then I'm stuck. I know it feels like I'm not listenning, thing is, I don't understand what I'm supposed to do when you say "do a large signal analysis"..... sorry about that. Anyway I'm going to read Parzen's book, I'm sure it will help, thank you. |
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