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Simulators >> Circuit Simulators >> Monte Carlo simulation methodology
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Message started by Aman on Apr 5^th, 2013, 5:45pm

Title: Monte Carlo simulation methodology
Post by Aman on Apr 5^th, 2013, 5:45pm

I have a rather fundamental question regarding Monte-Carlo simulation using Spectre. And I would like to use a Band-gap circuit as a reference design, as it would include a Bjt, resistor and MOS elements in the same design, and maybe designers have different experiences with those elements. The models support simulation of process and mismatch (globalmc_localmc) and the simulated variation (with sufficient no. of samples) in the band-gap voltage should cover 3-Sigma variation seen at the foundry.
(Also, this is common with designers from a lot of big semicon companies; no one I came across uses the correlation parameter between devices for simulation as described by Don O’Riordan in "Recommended Spectre Monte Carlo Modeling Methodology".)
Now, my question is with so much variation covered under-the-hood by the same model(globalmc_localmc), what kind of process variation/mismatch is getting simulated and are different devices correlated to each other? For example, can there be a case where the differential pair of op-amp in BGR have the two devices at extreme process corners with x%-mismatch on top (should be an impossible event even with lot/wafer/die/intra-die variations)? Is there any correlation between a fast MOS corner and fast BJT/min resistor corner.
I know this has a lot to do with foundry data but would appreciate if someone could shed some light here?

Thanks,
Aman

Title: Re: Monte Carlo simulation methodology
Post by rfidea on Apr 6^th, 2013, 3:07am

About the correlation. This is controlled by the models provided by your foundry in the PDK. Some have correlations and some do not. If there is correlation you will get a good picture of you total yield over time.

About your worse case questions for the diff-pair. In princip yes, you could get a run for your monte-carlo having maximum process corner and maximum offset as well, even if it is unlikely. But in my opinion monte-carlo simulations should not be used for finding worse case figures. Monte-carlo runs should be used for calculating the sigma of your distribution. Then you can calculate your yield depending on the distance to your spec.

For example, your bgr maybe have an average output voltage of 1.220V. Your spec says +/-15mV. Let say you run 1000 mc runs and get a sigma of 5mV. Then you can say that your bgr will meet spec with 3 sigma, which is a yield of 99.7%.

This does not say anything of worse case, your should use process corners for that.

Another way to put this is that your mc yield does not says that every batch of your circuit will have a good yield, then process corners needs to be used. But mc yield will tell you the yield over many batches.

Title: Re: Monte Carlo simulation methodology
Post by Aman on Apr 8^th, 2013, 5:26pm

Rfidea Thanks!! for the explanation. I have few follow-up questions from your answer
and would appreciate some more guidance.

1) Break-down of the local/global variation on a qualitative basis?
How much variation would be accounted in local mismatch vs global mismatch.
Example (intra-die+ die-die, same wafer) = local mismatch
(lot + wafer) = global mismatch
(1 wafer) = 1 process corner, all dies
Is there any such correlation or just an aggregate distribution?
2) Approach of running Monte-Carlo's?
This comes from the newer sub-nano models where process corner comes with its own
3-sigma variation, compared to older models with 3-sigma around typical corner.
Example, (tt+3-sigma1) compared to (tt/ss/ff/fs/sf+3-sigma2) assuming no particular
bias in the latter, where obviously (sigma1 > sigma2). What is your strategy to simulate
say a BGR in this case for the worst-case? (If my understanding is correct you would
take the process corner with least margin and run a local mismatch to simulate this, please
do correct me.)

Thanks,
Aman

Title: Re: Monte Carlo simulation methodology
Post by rfidea on Apr 14^th, 2013, 1:39pm

1. Hard to say any accurate. It depends on the component type and parameter in question. The design manual should give a clear answer. But numbers as 10-15% lot to lot and 2-3% on one chip. But the mismatch on one chip depends very much on component size, larger components match better. Usually there is difficult to get any numbers how the mismatch varies with the distance between two components that should match.

2. I have not used that type of technology. I do not understand the basics on it. Does the sigma variation on one specific process corner just handles the mismatch? I can understand that different corners has different mismatch. I guess simulating the corner closest to the limit is the worse also for mismatch.

Title: Re: Monte Carlo simulation methodology
Post by Aman on May 15^th, 2013, 4:43pm

Thanks!!