The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Common centroid/Interdigitized layout LVS issue
https://designers-guide.org/forum/YaBB.pl?num=1365966105

Message started by sami on Apr 14^th, 2013, 12:01pm

Title: Common centroid/Interdigitized layout LVS issue
Post by sami on Apr 14^th, 2013, 12:01pm

I am new to the idea of common centroid layout. Although I have studied various configurations of common centroid layout of differential pairs but every time I try implementing a configuration I get LVS errors. I have some basic questions to ask about common centroid layout design which I hope will help many other beginners as well.
1) Let me have a differential pair (A & B) with 20um/1um size of each MOS, now I want to implement the simplest possible configuration of interdigitization.i.e ABBA. I want to know to create two instances of A do I have to use multiplier or finger parameter of the MOS or shall I manually create 4 MOS each with size 10um/1um? When I use multiplier or finger parameter it gives only one solid instance in the layout with multiple drains/sources/gates or gates respectively.
2) Therefore I manually use 4 different MOS and simulate them in schematics. See the figure (cc1) below. To implement the configuration ABBA, I import all the four instances and create the layout as shown in cc2. But it gives LVS errors saying devices do not cross match. Why do parallel MOS with all terminals connected give us LVS errors? Am I following the right procedure for common centroid layout?
3) Please help!
[img][/img]

Title: Re: Common centroid/Interdigitized layout LVS issue
Post by sami on Apr 14^th, 2013, 12:03pm

Here is the schematic

Title: Re: Common centroid/Interdigitized layout LVS issue
Post by rfidea on Apr 14^th, 2013, 12:15pm

In the layout there is one common bulk node but in the schematic there are two bulks connected to nodes s1 and s2.

(The circuit is not a differential stage, it is two pmos source followers.)

Title: Re: Common centroid/Interdigitized layout LVS issue
Post by sami on Apr 14^th, 2013, 11:21pm

Thanks rfidea, You are right i am using an nwell tech and needed to connect the bulk to vdd. I have done it and there are no LVS errors.