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Design >> Analog Design >> DLL questions
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Message started by Evgenii on Apr 22^nd, 2013, 7:45am

Title: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 7:45am

Hi Folks! :)
Maybe this post more suitable for Digital Design, but anyway i'm try...
I'm new in design of Delay Locked Loop, and i already have schematic solution .
After simulation i see some strange behavior, which i can not a explain...
First of all, criterion of lock DLL (startup time) is absence of pulses (pulses are generated by PD), these pulses 'tells' to CP in which direction needs to realign VCDL. But on low frequences (some corners) i see that both pulses are presented in end-of-simulation and NO trend to decreasing one of them..What is it? Autooscillations of DLL? How to explain this problem and to solve...To solve I tried to increase capacitor in CP circuit, anyway it blindest solution...
On high frequences i see absence one of pulses, is good, but another pulse no disappear, he decreased to final amplitude. I think that is no problem, if propose, what she is smaller than treshold of transistor, and CP doesn't work with this amplitude.
I some disapointed :(, may all of this artefact of transients simulation, but precision is highest... May be is my misunderstanding in optimal parameters of CP pull up/pull down current, CP capacitor , frequency ranges of DLL.
Thanks for help! :)

Title: Re: DLL questions
Post by raja.cedt on Apr 22^nd, 2013, 8:00am

Hello,
Please explain in-detail, better show show some PD,CP results or up and down pulse....without it is very tough to imagine your problem. Any how i guess you have problem with your PD, so please run a transient Sim and check weather output is in-phase or not. If they are not then i would say you better replace PD with-some verilog-A model and check the sim.

Raj.

Title: Re: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 8:24am

Thanks!
NOLAP and GAP pulses are presented in every clock. This Fig for PSRR, some strange behavioral after VDD step from 3.3 to 3.6V (no pulses). GAP and LAP between 1 and 8 (first and last output pulses) looks like "swing" :)

Title: Re: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 8:35am

with Ideal CP is eliminated problem with "swing" but at highest frequency part of NOLAP still try to realign VCDL...BTW, whats wrong may be with my PD, is only simple logic with NAND and NOR gates...
Below i attach both CP

Title: Re: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 8:54am

M10, M4 - for fast startup. Divider on diods has no influence on charge/discharge process. In 'swing' average of V_IBIAS is still constant.

Title: Re: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 9:12am

And last spam today :)
Higher frequency. NOLAP has trends to saturation and no disappear...

Title: Re: DLL questions
Post by Evgenii on Apr 22^nd, 2013, 11:05pm

Sorry :)! What is mean: "check weather output is in-phase or not..."