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Design Languages >> Verilog-AMS >> Load Resistance of Two-Port
https://designers-guide.org/forum/YaBB.pl?num=1366718836

Message started by oner on Apr 23^rd, 2013, 5:07am

Title: Load Resistance of Two-Port
Post by oner on Apr 23^rd, 2013, 5:07am

Hey, I m a beginner in Veriloga and new in this Forum.
I am trying to build an amplifier. My Problem is that the gain of the Amplifier is dependent on the load resistance.
I tried to set the output voltage (V(out) <+1) for getting the output current (r_load = V(out)/I(out)), but this gives me an error : "No DC convergence."

Can you give me an idea to solve this problem ?

Regards

Title: Re: Load Resistance of Two-Port
Post by boe on Apr 24^th, 2013, 2:39am

oner,
to get the voltage of a node, you do not need to have a contribute statement to this node.
- B O E

Title: Re: Load Resistance of Two-Port
Post by oner on Apr 25^th, 2013, 2:17am

Thanks for the reply.

I tried it with a current source and the problem is solved.

Oner