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Design >> Analog Design >> DLL design using Maneatis architecture (All phases are not equally spaced ) )
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Message started by saurabh3488 on Apr 23^rd, 2013, 7:16am

Title: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by saurabh3488 on Apr 23^rd, 2013, 7:16am

Hi,

I am designing a DLL for 200MHz (5nsec) clock. The requirement is to generate 9 phases of clock (each separated by 0.55nesc)
I have used Maneatis architecture to design Delay cell (Replica Bias).
DLL is working fine but the problem is that all the phases are not equally separated means there is finite (around 20psec) difference in delay between consecutive stages.

please help me regarding this problem ...

Title: Re: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by raja.cedt on Apr 23^rd, 2013, 9:35am

Hello,
is loop filter voltage is going to all delay cells without any drop?? Please check 9-delay cell's control voltage.And verify input common mode of all delay cell and signal swing. Please provide some more data. Are you working on schematic level or parasitic extracted? I guess you are sharing replica for all the delay cells so check is op-amp out is going to nmos without any drop....

Raj.

Title: Re: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by saurabh3488 on Apr 23^rd, 2013, 10:50am

Hi Raj.

I am working on schematic level , so i don't think droop in voltage comes into play and all the delay stages are similar means the common mode of all the stages are same.
still the problem is there like each stage should contribute 0.55nsec (5nsec/9). but they are giving different different delay.
and the min to max delay is around (20psec)

Title: Re: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by raja.cedt on Apr 23^rd, 2013, 12:50pm

hello,
then what is different parameter among delay cells, is final stage connected directly to PD or any buffer. May be post the result we might catch some thing...You better test delay cell without simulating the whole loop. Just a make a test-bench, in which only cascaded 9 delay cells and and check the delay for several control voltages...

Thanks,
Raj.

Title: Re: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by saurabh3488 on Apr 24^th, 2013, 12:24am

Final stage is connected to a dummy stage and PD.
and also 1st stage is connected to PD.
i kept a cap load equal to input of PD to all the stages.

Here is the result : The delay between two consecutive stages.
(Ideal should be 5.55E-10 (0.55nsec))

from result attached we can see than there is delay difference
like max to min is around 8psec.

Title: Re: DLL design using Maneatis architecture (All phases are not equally spaced ) )
Post by loose-electron on Apr 24^th, 2013, 8:43pm

is the same delay error seen in multiple devices? (indicates systematic problem in the design)

or is the delay unique to each chip (indicates matching and offset issuees)

From there:

Is the variance you see, the expected range of mismatch in the devices and the rise fall characteristics correlate? (i.e. if you expect 20mV mismatch, and the rise fall time is 20psec does that correlate to the 20mv mismatch?)