The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> CMOS current mirror circuit https://designers-guide.org/forum/YaBB.pl?num=1366787525 Message started by Priya  M K on Apr 24th, 2013, 12:12am

Title: CMOS current mirror circuit Post by Priya  M K on Apr 24th, 2013, 12:12am I have taken a paper on Current mirror circuit from IEEE as my main reference paper for my MTech thesis. The paper is attached hereby. I have some doubts regarding the design.   1. In the paper it is said that M6 & M7 are diode connected. So is it the source of M6 connected to the gate of M5? Is it possible to connect the drain of pmos to Vdd?   2. In the design it is said that all the transistors have equal W/L ratio. Can you please tell me how to design the circuit?   3. I have tried to simulate the circuit using NG Spice. Is it possible to do so? If not please suggest an open source tool for simulation.   4. In the circuit the drain of M5 is left open. During simulation what should i add at the drain of the M5 to complete the circuit and do the analysis.   5. How can i see the current vs voltage characteristics in NG spice?   6. Can you please provide the netlist for simulating the circuit in NG spice? Could you please help me in solving the issues? Can you please give a description about designing W/L for current mirrors and also viewing the outptut characteristics of the circuit, (Iout vs V graph).[/img] please refer fig 3

Title: Re: CMOS current mirror circuit Post by RobG on May 13th, 2013, 10:37am Diode connected generally means the gate-drain are connected. As you noticed, the schematic has gate-source connected. I'm guessing M5 and M6 are depletion mode devices so they act like current sources even when Vgs=0. This can be done, but I personally prefer current sources less sensitive to process. You should learn about designing circuits and building your own netlist if this is a major part of your thesis.  ;)

Title: Re: CMOS current mirror circuit Post by boe on May 14th, 2013, 9:44am RobG wrote on May 13th, 2013, 10:37am: ... As you noticed, the schematic has gate-source connected. I'm guessing M5 and M6 are depletion mode devices so they act like current sources even when Vgs=0. ... The connection of M6/7 may also be an error in the figure. - B O E

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