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Design >> Analog Design >> How to Increase the sampling frequency of Pipelined ADC
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Message started by amitesh on May 6^th, 2013, 12:07am

Title: How to Increase the sampling frequency of Pipelined ADC
Post by amitesh on May 6^th, 2013, 12:07am

hello
I have designed a pipelined ADC that is working upto 50MSPS. Now same design i want to scale up and want to make it work at 100MSPS.
so which block, i have to redesign and which block i have to modify.

thanks
amitesh

Title: Re: How to Increase the sampling frequency of Pipelined ADC
Post by carlgrace on May 7^th, 2013, 2:14pm

You're going to have to revisit and re-specify each block.

First, figure out what is limiting your speed to 50 MS/s? Is it the clock generator, settling in the MDAC? The speed of your comparator? Until you can answer that question it is hard to give suggestions!

Also, depending on your process you have to ask yourself if 100 MS/s is do-able.

Title: Re: How to Increase the sampling frequency of Pipelined ADC
Post by amitesh on May 7^th, 2013, 9:10pm

carlgrace wrote on May 7^th, 2013, 2:14pm:

thanks alot,
I have designed 50MS/s ADC in umc130nm so i thing process is not going to make any problem.
My Comparator, clock generator and Sub-ADC is working upto 250MHz. so i thing that is not a problem.
Only MDAC is hurdle, Should i redesign OTA?
or i change Cs and Cf.

and also upto 100MS/s, what is the best way take references for MDAC and Sub-ADC. it is through internal Bandgap or taking external with huge bypass capacitor outside the chip?

amitesh

Title: Re: How to Increase the sampling frequency of Pipelined ADC
Post by carlgrace on May 8^th, 2013, 9:57am

130nm is fine for 100 MS/s. So what to change to speed it up really depends on your specs. If you can deal with more DNL and INL, sure you can reduce your cap sizes. You can also increase your OTA current if you need more speed. Watch out for reduced open-loop gain in that case. It's possible you'll need to redesign your OTA but you wont know until you really analyze your specs. If your gain and cap sizes are already set to get the accuracy you need, you'll have no choice but to re-design your OTA for more GBW. That's going to cost you power, but there really isn't a way around it. It *may* be more efficient to put in a digital calibration system to relax the interstage gain requirements, but that may be more trouble than it's worth.

As for the references, there are two schools of thought there. One is to design a reference buffer so fast that it settles in half a clock cycle. Another is to put a big enough off-chip cap on the reference that it doesn't move more than a fraction of an LSB when you are operating.

Personally, I've had better luck using an off-chip cap. Just be aware that now you have a resonant circuit (including bondwire or bump inductance) in your reference path. You must simulate it thoroughly (post-layout) to make sure it doesn't peak at a troublesome point or even oscillate.

I don't recommend using a completely off-chip reference... it makes the board design harder because any interference on your reference goes right to the output. I would recommend putting a bandgap on the chip but be sure it can be bypassed if it fails.

Title: Re: How to Increase the sampling frequency of Pipelined ADC
Post by amitesh on May 8^th, 2013, 10:20pm

thanks carlgrace Sir,

i have already increased the OTA current to increase the UGB.
Dear I have read alot of papers for the specification of OTA. but Every where there is differences in formula. So can please give me the required OTA specs for 14 Bit, 100MSPS Pipelined ADC with Dynamic CMFB. And also how can i do the AC analysis with Dynamic CMFB. Is it only by putting equivalent resistance or any other method. Currently i am deciding gain and phase by transient only.

In my design Only Onchip Reference is the problem. So can you suggest Some good paper and thesis for on- chip reference design.

thank sir.
with regard
amitesh