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Design Languages >> Verilog-AMS >> Port pattern matching excitation
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Message started by ChrisV on May 10^th, 2013, 6:43am

Title: Port pattern matching excitation
Post by ChrisV on May 10^th, 2013, 6:43am

Hi,
I have a test bench driver (written in Verilog-AMS) with multiple output ports (some of them buses, some single bits).
I need to be able to scan through all possible output values for a subset of some of these ports.
I don't however want to hard code the ports that I will excite.
I would prefer to say cycle though all the possible binary values only for those ports whose name starts with let's say "LO_CALIB*".
Could someone suggest a way of going about that ?

Thanks,
Chris