The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> High-Speed I/O Design >> Delay Locked Loop Design https://designers-guide.org/forum/YaBB.pl?num=1368802335 Message started by saurabh3488 on May 17th, 2013, 7:52am |
Title: Delay Locked Loop Design Post by saurabh3488 on May 17th, 2013, 7:52am Can Loop Filter in Delay locked loop cause stability issue. |
Title: Re: Delay Locked Loop Design Post by Jeffrey987 on Mar 12th, 2015, 11:08am Typically a DLL is a first order type 1 system. You have to take into account that your phase detector is a sampled system and you are approximating a continuous s-domain system with a discrete z-domain system. Therefore your loop bandwidth should not be too large fref/10~20. This implies constrains on your loop cap in combination with Kvcdl and Icp. |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |