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Design >> Analog Design >> biasing transistor for LNA
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Message started by neo dili on May 29^th, 2013, 12:14am

Title: biasing transistor for LNA
Post by neo dili on May 29^th, 2013, 12:14am

Hi,
I am newbie in RF IC design and presently working to design an LNA at 2.4GHz.I have a doubt .I used a cascode arrangement with current mirror for biasing.the problem is once I did the dc analysis and printed the dc operating point in cadence virtuso(UMC 180nm tech) the value obtained for Cgs=-124.3f and gm=34.74m.the transition frequency ,wt=gm/Cgs=279G .is this value very large since Ls=Rin/wt and if Rin=50ohm,Ls will be 0.179nH !!!!
where shall be the mistake?????

Thanks in advance

Title: Re: biasing transistor for LNA
Post by neo dili on May 29^th, 2013, 9:00pm

I am also attaching my work,kindly take a look and help out