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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> How to Generate a Rectangular Pulse with Different Amplitudes https://designers-guide.org/forum/YaBB.pl?num=1369925830 Message started by Kevin Finn on May 30th, 2013, 7:57am |
Title: How to Generate a Rectangular Pulse with Different Amplitudes Post by Kevin Finn on May 30th, 2013, 7:57am Hi everyone, I've been trying to implement the following with Verilog A; however, I couldn't make it work thus far. What I wanna do is basically generate a rectangular pulse with more than 2 different amplitudes. For example, the amplitudes I want my pulse to have are 5, 3, 1, and -1 (in voltage). During each unit interval, which's let's say 50 ns, I want my pulse to be equal to one of the abovewritten values. I expect to code something like the following: Code:
However, the second line overwrites the first line, the third line overwrites the first two lines, and so on and so forth. Could you please help me as to how I can code such a pulse in Verilog A? Thanks in advance! |
Title: Re: How to Generate a Rectangular Pulse with Different Amplitudes Post by Ken Kundert on May 31st, 2013, 1:16am Try using @timer rather than @above. Use the second argument on the timer function to implement periodicity. -Ken |
Title: Re: How to Generate a Rectangular Pulse with Different Amplitudes Post by Kevin Finn on May 31st, 2013, 2:24am Thanks for your response, Ken! I actually had tried the @timer event before and couldn't make it work either. Could you please tell me what's wrong with the following code? V(out) seems to be zero at all times when I simulate it. Code:
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Title: Re: How to Generate a Rectangular Pulse with Different Amplitudes Post by Ken Kundert on May 31st, 2013, 10:19am You have not given enough of the model to see the problem. Please give the entire module. -Ken |
Title: Re: How to Generate a Rectangular Pulse with Different Amplitudes Post by Kevin Finn on Jun 3rd, 2013, 2:10am Thanks for your response, Ken! Now, it's working, although I didn't get what the problem was before. I'm learning Verilog-A from scratch, so perhaps I did something nonesense. Code:
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