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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Phase Detector Design for Delay Locked Loop https://designers-guide.org/forum/YaBB.pl?num=1370671347 Message started by saurabh3488 on Jun 7th, 2013, 11:02pm |
Title: Phase Detector Design for Delay Locked Loop Post by saurabh3488 on Jun 7th, 2013, 11:02pm Hi All, I have a very basic question, is the locking time of loop depends on the types of Phase detector, means if i use PD using static logic (NAND gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason). please replay. Thanks |
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