The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Power down, voltage level issues
https://designers-guide.org/forum/YaBB.pl?num=1370855680

Message started by Pictou on Jun 10^th, 2013, 2:14am

Title: Power down, voltage level issues
Post by Pictou on Jun 10^th, 2013, 2:14am

Hello,

Before asking for help, I would like to present the situation a little.

I'm working on an amplifier. The amplifier is working fine, but there is a problem. My supply voltage is 5V and the transistors I use to amplify can only sustain 3.3V.

During power up, I fixed this voltage issue by using a cascode.
However, during power down, I have no current in my cascode current mirror, so my cascode doesn't shift the voltage anymore, and several transistors are now exposed to 5V (voltage between drain and source for instance).

Please find my simplified schematic in the following pdf file :
http://www.pdfhost.net/index.php?Action=Download&File=b46298d3d8a7de2500262eb3f17ef69d

So, the problem is for instance, Transistor 1 (next to INPUT). During power down, the drain is at 5V and the source is at 0V.
I tried to find solutions, but everything I found wasn't validated because I've been told that with such low current, simulations are not reliable (or at least we can't reproduce it on sillicon).

My question is the following, how would you deal with this issue? knowing that, as I am in a power down state, consumption should be minimal. I have no strict restriction on surface of sillicon but I don't think a LDO to shift the voltage from 5V to 3.3V is acceptable (for instance).

I tried to find something on google, but nothing come up, I don't even know which key words to use.

Thank you for your help!

Title: Re: Power down, voltage level issues
Post by carlgrace on Jun 18^th, 2013, 1:33pm

Have you tried putting switches in series with your main current path between the current mirror and the 5V supply. If you opened up those switches before you removed the bias current then the current mirror wouldn't see 5V.

Title: Re: Power down, voltage level issues
Post by Pictou on Jun 19^th, 2013, 7:49am

Hello, thank you for your help.

I'm not sure I understand what you mean. The switches would be on the left or the right side ?

I tried putting switches, thing is, in a power down state I have so low current that I can't tell at what voltage the nodes between transistors will be.
Right now I decided to create an extra voltage level, for instance 3.3V that I can insert in the schematic, but it consumes a lot of current... I hope there is another solution.

Title: Re: Power down, voltage level issues
Post by Kevin Aylward on Jul 6^th, 2013, 2:49am

A general technique to stop nodes floating high when, for examples, their cascade is turned off, is to catch those leakage currents via a diode to a reference voltage. Often that reference voltage is available, if not, a string of diodes, or mos connected diodes to the supply or ground as a zero current clamp, may work. Sometimes a reverse diode on the gate source of the cascode transistor is enough to steer the leakage to a suitable point. Depends on the corners and temperatures whether the protected nodes can be taken a bit higher than usual operating voltage, but less than their voltage ratings.

Title: Re: Power down, voltage level issues
Post by Pictou on Jul 8^th, 2013, 12:33am

I tried using the leakage current, but cadence don't seem to like it. There is a warning saying that I should lover the gmin, and depending on the value I give to gmin, results are very different.

Maybe I'm doing it wrong, do you know where I could find more information about the method you are talking about? (on the internet if possible).

The oxide thickness of the mos is about 2.2nm, I'm not even sure I will have enough leakage to hold the corner simulations.