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Design Languages >> Verilog-AMS >> Error during simulation
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Message started by fuzail on Jun 16^th, 2013, 7:37am

Title: Error during simulation
Post by fuzail on Jun 16^th, 2013, 7:37am

Hi all,

I have made verilog-A model of switches and using them in the circuit to perform simulation. Here spectre gives me error like "too few terminals given (3<4)".

Here i have two types of switches one is 3 terminal switch (vin,vcontrol,vout) and other is four terminal switch (vref+,vref-,vcontrol,vout) .

Operation of 1st switch is simple if vcontrol>vth then switch closed else open. (vth is given as parameter in code)

Operation of second switch is
if vcontrol>vth vout=vref+
else vcontrol <vth vout=vref-

I made symbols of both n using in switched integrator circuit along with fully differential-opamp but giving the error as described above.

If switch2(four terminal switch) is removed spectre is not showing any error..... Any help on this would be appreciated

Thanks--
Fuzail

Title: Re: Error during simulation
Post by rfidea on Jun 16^th, 2013, 12:54pm

I have a longshot... Have you the same name of the switches in the two veriloga codes? Easy done if one cell originates from a copy of the other one. I have done that mistake myself a long time ago and got the same problem.