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Design >> RF Design >> Capacitance multiplier in loop filter of a PLL
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Message started by harpoon on Jun 28^th, 2013, 2:46am

Title: Capacitance multiplier in loop filter of a PLL
Post by harpoon on Jun 28^th, 2013, 2:46am

Hi all,

I am implementing an on-chip cap multiplier to so that the loop filter of my PLL can be integrated onto the chip. I have seen several papers on this ... but no one seems to address the issue of reduced resistance across input voltage (vco tuning voltage) range ... i.e. when the current mirrors go out of saturation.

Does anyone have any comments on this ?

The circuit is shown here ...

Thanks.

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by harpoon on Jun 28^th, 2013, 2:52am

Here are some equations ...
Ceff = (1+B) * Ci

Rin = 1/go of the PMOS and NMOS cascode at node A

Thanks for having a look ...

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by Kevin Aylward on Jul 7^th, 2013, 2:01am

Capacitance multipliers are those sort of topologies that many like to write impressive reading papers about, but arguably, have little practical use in these real 3 universes, in my opinion. Typically, issues are either noise being multiplied up by the same factor and/or signal handling going down by the same ratio. If it were me, I would look for another solution.

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by harpoon on Jul 8^th, 2013, 3:14pm

Hi Kevin,

Thanks for your comment ...

However, I am pretty sure this has been implemented in silicon before, esp in PLLs ... anyone care to discuss their experience ?

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by tm123 on Jul 9^th, 2013, 8:54am

harpoon,

If this PLL is of the fractional N type, I would be extremely concerned about this cap multiplier increasing fractional spurs. In general the charge pump nonlinearity is the main issue but anything nonlinear in the loop will increase spurs.

I agree with Kevin in that I have seen papers mentioning this approach, but the added noise/nonlinearity/stability issues will probably end up outweighing any benefit.

Hope this helps.

Tim

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by Kevin Aylward on Jul 9^th, 2013, 11:06am

Yes, I am sure the are many that implement questionable designs in silicon :-)

Consider an amp set to a gain of 100 with the cap across it to increases its effective value. Its input via the resistor, with the output taken from the cap/amp input junction as a filter. Although the output of the amp is never looked at, it still swings the input volts multiplied by 100. If the input DC moves 0.5V, the output wants to move 500V which it can’t, so it won’t. Current mode gets deeper into the S*&£. Its not worth the agro, trust me.

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by tm123 on Jul 9^th, 2013, 11:59am

Kevin,

I understand your explanation. I think we are in agreement that the benefit of a cap multiplier in this case is not worth the tradeoffs of worse noise, worse linearity and worse stability performance.

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by Kevin Aylward on Jul 9^th, 2013, 12:04pm

So you agree 100 X 0.5 is 500 :)

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by tm123 on Jul 9^th, 2013, 12:05pm

Only for large values of 0.5 ;D

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by harpoon on Aug 13^th, 2013, 4:31am

it is for a simple integer-n PLL ...

thanks for the comments ... I think I'll just use a bigger real cap ! (and tweak other loop params).

Title: Re: Capacitance multiplier in loop filter of a PLL
Post by loose-electron on Aug 18^th, 2013, 11:31am

harpoon wrote on Aug 13^th, 2013, 4:31am:

it is for a simple integer-n PLL ...

thanks for the comments ... I think I'll just use a bigger real cap ! (and tweak other loop params).

Generally there are lots of knobs available to adjust.

Scale the charge pump current down and see what you can do to get the C down.