The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Using decoupling/bypass capacitor https://designers-guide.org/forum/YaBB.pl?num=1372577269 Message started by Evgenii on Jun 30th, 2013, 12:27am

Title: Using decoupling/bypass capacitor Post by Evgenii on Jun 30th, 2013, 12:27am Hi folks! Frequently designers are using decoupling/bypass capacitor in analog design. For instance, in current mirrors: from common gates point to GND/VDD or  from biasing point of cascode to GND/VDD. It good practice for filling empty places of layout, for example  in standard cells =). But, really, how much value of capacitor is needed? Is hard to predict, where is standard cell will be used. Say, what a generator will be closed to this cell?... Moreover, the decoupling/bypass capacitors in parallel with transistors with some gm and have ESR and ESL parasitics... Please, explain for me simple (or not) method for calculate required values of decoupling/bypass capacitor (say for protection from  generator on few MHz) or some common method for STD cells... Otherwise, using the capacitor for this case is only eating of chip area... >:( First of all, please  explain me nature of bypass/decoupling protection... Thanks! :)

Title: Re: Using decoupling/bypass capacitor Post by Ken Kundert on Jun 30th, 2013, 9:50pm I have just such a document for board design. Perhaps that will help. http://www.designers-guide.org/Design/bypassing.pdf -Ken

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