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Design >> Mixed-Signal Design >> PLL simplification
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Message started by aaron_do on Jul 2^nd, 2013, 11:47pm

Title: PLL simplification
Post by aaron_do on Jul 2^nd, 2013, 11:47pm

Hi all,

just wondering, what kind of simplifications can I make to my PLL to speed up the simulation while still getting an accurate measure of the settling behavior? For example, can I do a behavioral model of the VCO+dividers (group them into one model)? I'm thinking to use verilog-a for this, but I'm worried it won't be accurate because the VCO has a nonlinear kvco.

One more thing, if I do this, what kind of trade-off will I be making?

thanks,
Aaron

Title: Re: PLL simplification
Post by tm123 on Jul 9^th, 2013, 8:40am

Hi Aaron,

Is your settling time spec defined from power up or when frequency hopping?

It may be difficult to simulate a closed loop PLL especially at the transistor level with Spectre/SpectreRF. If you have a large feedback divider ratio and a lot of digital circuitry (PFD, frequency dividers) the sim time can blow up significantly (maybe you are already experiencing this).

In the past I have converted all digital circuitry to verilog code and got a significant improvement, but the sims can still take 24 hours or more.

If you have a strict settling time spec, I think you need watch out for saturating/trioding charge pump current sources, cycle slipping if the ratio of comparison frequency to loop bandwidth is high, and nonlinear KVCO as you said.

Hope this helps.

Tim

Title: Re: PLL simplification
Post by aaron_do on Jul 9^th, 2013, 5:47pm

Hi Tim,

thanks for the advice. Actually I tried implementing a VCO+ divider with a nonlinear Kvco, and although the settling time was about the same, the transient curve of the control voltage was not the same.

Anyway for my application, the PLL is quite simple, and its possible to complete the transient analysis overnight. I just wanted to see if it were possible to run the simulation even faster.

regards,
Aaron

Title: Re: PLL simplification
Post by loose-electron on Aug 18^th, 2013, 12:00pm

aaron_do wrote on Jul 9^th, 2013, 5:47pm:

Overnight is not surprising

All behavior PLL (I've done these in Verilog AMS) will close and run in 20 mins, but no transistors. Depends a lot on your divide ratios, where the Fvco >> Freference the closed loop runs can take a while.