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Design Languages >> Verilog-AMS >> Modeling Gm(t) of a hard-limiter Voltage to Current converter.
https://designers-guide.org/forum/YaBB.pl?num=1373052148

Message started by Ricky Chen on Jul 5^th, 2013, 12:22pm

Title: Modeling Gm(t) of a hard-limiter Voltage to Current converter.
Post by Ricky Chen on Jul 5^th, 2013, 12:22pm

Dear All,
I have modelled a hard-limiter V-to-I converter (Gm(t)).
I want to add a noise white current noise Source in parallel to it as I= 4*K*T*Gm(t).
Can anybody please tell how to write the code for that ?

My hard-limiter V-to-I converter (Gm(t)) code is as below:-

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
inout in,out;
parameter real vtrans = 0;
parameter real tdelay = 0 from [0:inf);
parameter real trise = 1p from (0:inf);
parameter real tfall = 1p from (0:inf);
parameter real Gm=-5m;
electrical in,out;
real vout_val;
analog begin

@ (cross(V(in) - vtrans, 1)) vout_val = 1;
@ (cross(V(in) - vtrans, -1)) vout_val = 0;

I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall);
end
endmodule

Kind Regards,

Title: Re: Modeling Gm(t) of a hard-limiter Voltage to Current converter.
Post by Geoffrey_Coram on Aug 2^nd, 2013, 8:51am

Wouldn't it just be

I(out) <+ white_noise(4 * `P_K * $temperature * Gm);

?