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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Problem in creating logic to electrical connect module in verilogams https://designers-guide.org/forum/YaBB.pl?num=1373404376 Message started by indra0804 on Jul 9th, 2013, 2:12pm |
Title: Problem in creating logic to electrical connect module in verilogams Post by indra0804 on Jul 9th, 2013, 2:12pm Hi, I am trying to make a logic to electrical connect module that can convert logic ( '1' or '0') at the input side to electrical pulses at the output side, implementing in verilog-ams, its required for one of the project that I am doing. But, the problem that I am having is that, its running and simulation is taking place, but irrespective of whether I give '1 or a logic '0'', the output is staying at 818.18mV. My Vhigh= 1.8 V and Vlow= 0v. I am attaching the code that I am trying to implement.... (Taken from the designers guide only....... link: http://www.designers-guide.org/Books/dg-vams/ch4/ch4-listing18.tgz) // Logic to Electrical Connect Module // // Version 1a, 1 June 04 // // Olaf Zinke // // Downloaded from The Designer's Guide Community (www.designers-guide.org). // Post any questions on www.designers-guide.org/Forum. // Taken from "The Designer's Guide to Verilog-AMS" by Kundert & Zinke. // Chapter 4, Listing 18. `include "disciplines.vams" `timescale 1ns / 10ps connectmodule d2a (out, in); parameter real v0 = 0.0; // output voltage for a logic 0 (V) parameter real v1 = 5.0; // output voltage for a logic 1 (V) parameter real vx = 2.5; // output voltage for a logic x (V) parameter real vz = 5.0; // output voltage for a logic z (V) parameter real r0 = 1k from (0:inf); // output resistance for a logic 0 (Ohms) parameter real r1 = 1k from (0:inf); // output resistance for a logic 1 (Ohms) parameter real rx = 100 from (0:inf); // output resistance for a logic x (Ohms) parameter real rz = 1M from (0:inf); // output resistance for a logic z (Ohms) parameter real tr=1n from [0:inf); // rise time (s) parameter real tf=1n from [0:inf); // fall time (s) input in; output out; logic in; electrical out; real v, r; assign in = in; initial begin case(in) 1'b0: begin v = v0; r = r0; end 1'b1: begin v = v1; r = r1; end 1'bx: begin v = vx; r = rx; end 1'bz: begin v = vz; r = rz; end endcase end always @in begin case(in) 1'b0: begin v = v0; r = r0; end 1'b1: begin v = v1; r = r1; end 1'bx: begin v = vx; r = rx; end 1'bz: begin v = vz; r = rz; end endcase end analog V(out) <+ transition(v, 0, tr, tf) + transition(r, 0, tr, tf)*I(out); endmodule I am trying to implement it in cadence ADE with AMS simulator. Regards, Indrajit |
Title: Re: Problem in creating logic to electrical connect module in verilogams Post by boe on Jul 15th, 2013, 7:08am Indra0804, the code posted is for 5V, not 1.8V. Please provide v and r for both values at the input. - B O E |
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