The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Monte-Carlo simulation and writing to file from VerilogA
https://designers-guide.org/forum/YaBB.pl?num=1373526711

Message started by sutapanaki on Jul 11^th, 2013, 12:11am

Title: Monte-Carlo simulation and writing to file from VerilogA
Post by sutapanaki on Jul 11^th, 2013, 12:11am

I'm running 100 MC simulations from ADEXL. My setup includes a verilogA block which among other things also writes results to a file. The problem I'm having is that in my case 10 MC runs use the same process and each one of them overwrites the content of the file from the previous run. So, at the end I don't have the results from all 100 MC runs but maybe just from the last 10. I can't have 100 separate processes running 100 MC runs because of licensing restrictions. Can anyone suggest a way to either have each MC run write to a separate file or how to use $fopen to append to a file and not overwrite it?
Thanks.

Title: Re: Monte-Carlo simulation and writing to file from VerilogA
Post by boe on Jul 15^th, 2013, 7:15am

Sutapanaki,
see Verilog-AMS L(anguage)R(eference)M(anual) (http://www.designers-guide.org/VerilogAMS/).
- B O E