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Design >> Analog Design >> 65nm vs 40nm noise performance
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Message started by aaron_do on Jul 22^nd, 2013, 8:01pm

Title: 65nm vs 40nm noise performance
Post by aaron_do on Jul 22^nd, 2013, 8:01pm

Hi all,

I am trying to port the design of a ring oscillator over from 65nm technology to 40nm technology, and I've run into a road block. I ran a noise simulation on a diode connected MOSFET (same size in both processes) with a fixed DC current flowing through both, and checked the noise voltage at the drain node. I noticed that for the 40 nm technology, the noise performance is about 3-4 times worse across the spectrum. Both technologies are from the same fab house, and I have tried several different transistors (lvt, nominal vt, dnw, IO) and all show a huge degradation in noise performance. I have also checked the gm of the devices and they are very close (within around 1%).

Does anybody know if this is a real effect?

thanks,
Aaron

Title: Re: 65nm vs 40nm noise performance
Post by raja.cedt on Jul 22^nd, 2013, 10:24pm

Hi aaron,
What you have observed is true for single transistor. In-general noise performance worsen in cmos scaled technology for both thermal as well as flicker noise corner. One simple reason could be for the same Gm, gamma (noise coefficient)will increase from 60 to 40nm. However this explanation is true for single transistor, where as for a vco noise depends on the actual transistor noise as well as conversion gain so difficult to comment for VCO.

Thanks,
Raj.

Title: Re: 65nm vs 40nm noise performance
Post by aaron_do on Jul 22^nd, 2013, 11:07pm

Hi raja.cedt,

thanks for the reply. Would I expect to see such a huge difference for a transistor alone (3-4x degradation)?

thanks,
Aaron

Title: Re: 65nm vs 40nm noise performance
Post by aaron_do on Jul 23^rd, 2013, 8:09pm

Hi.

After some investigation I found that it is the 65nm process which is wrong by about 4x. I just checked based on 8/3kTgm. So is there any way I can solve this problem? I guess its not a modelling issue but something to do with the simulator.

Thanks
Aaron

Title: Re: 65nm vs 40nm noise performance
Post by avlsi on Jul 26^th, 2013, 10:27pm

Hi Aaron Do,

8/3 KT gm is for long channel technologies.
If you look at the noise modeling for thermal noise in BSIM3V3 or BSIM4 Manual, you will know that drain current noise is no longer valid with 8/3 factor.
But you can get this constant from simulation as,
gamma=f(VDSAT,L)

What you can do is, extract gamma for 65nm and 40nm technology. I think this will tell the real story for the discrepancy.