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Design >> Mixed-Signal Design >> PLL noise contribution
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Message started by aaron_do on Jul 22^nd, 2013, 11:20pm

Title: PLL noise contribution
Post by aaron_do on Jul 22^nd, 2013, 11:20pm

Hi all,

I am modifying a PLL design which was purchased by my company from a respected design house, and I found some problems with the jitter. Basically, the ring VCO's oscillation frequency is controlled by its bias current using some kind of V-I converter connected to the loop filter.

Through simulation, I have found that most of the PLL's total jitter is coming from this V-I converter. This makes sense to me since the V-I converter doesn't benefit from the loop filter's filtering.

My question is, is it normal to have active circuitry in between the loop filter and the VCO, and how do you get around this issue?

thanks,
Aaron

Title: Re: PLL noise contribution
Post by raja.cedt on Jul 23^rd, 2013, 3:10am

Dear aaron,
1. Most of the ring oscillators were controlled through tail current of differential pair or tri-state inverter bias current,i guess this is very similar to your case(of course you have a specific v2i rather than inherent ).

2. i didn't understand why v2i converter doesn't benefit from filtering, if you look at the transfer function from control node to pll output it will be band pass function, so only around loop BW only noise appears at the output.

3. I have seen Few design's which has active circuits between control node and VCO,mostly they are level shift circuits.

Thanks,
Raj.

Title: Re: PLL noise contribution
Post by aaron_do on Jul 23^rd, 2013, 7:01am

Hi raj,

thanks for the info.

Quote:

i didn't understand why v2i converter doesn't benefit from filtering, if you look at the transfer function from control node to pll output it will be band pass function, so only around loop BW only noise appears at the output.

Well if I'm understanding the PLL properly (which is in doubt) transfer function from the control voltage to the output is Kvco/(1+LG). Ideally this is a high-pass right? So its good for filtering low-frequency noise. Well it seems that the noise beyond the loop unity gain bandwidth is quite poor. That's what I've concluded anyway.

regards,
Aaron

EDIT:
Maybe I can reduce KVCO and increase kΦ to compensate?

Title: Re: PLL noise contribution
Post by tm123 on Jul 23^rd, 2013, 7:58am

Aaron,

The ring oscillator VCOs I have seen are tuned by controlling differential pair tail currents as you described. I normally work with VCO noise referenced to the VCO output (instead of the control node), and when inserted into the PLL loop the noise transfer function is 1/(1+LG) which is indeed high pass.

With that being said, I think it makes sense that the V2I conversion causes a jitter increase outside the loop bandwidth and reducing the KVCO should help. Increasing the Kphi parameter could be done to return the loop bandwidth to its original value. I am not sure what flexibility you have in this design but it may be possible to increase the loop bandwidth at the expense of in band jitter and reference spurs. Again, I do not know what other performance constraints you are up against.

Hope this helps.

Tim

Title: Re: PLL noise contribution
Post by aaron_do on Jul 23^rd, 2013, 8:21am

Hi Tim,

Thanks for the help. I thought I might try and increase the loop bandwidth, but I think it is already set to 1/10 times the referenfe frequency so im worried about stability. I guess I should check again.

Aaron

Title: Re: PLL noise contribution
Post by tm123 on Jul 23^rd, 2013, 8:43am

Aaron,

I would certainly not recommend increasing the loop bandwidth if it is already 1/10 of the reference frequency. Theoretically it can be done but you need to analyze the loop as a sampled system which is much more complicated. You probably already know, but all PLL loops are technically sampled systems and if you keep the loop bandwidth low enough compared to the reference frequency you can cheat and analyze the loop as a continuous time system. If you are interested there are good references written by Jim Crawford at www.am1.us. He has written text books and papers on the subject of analyzing PLLs as sampled systems.

Tim

Title: Re: PLL noise contribution
Post by aaron_do on Jul 23^rd, 2013, 5:56pm

Hi Tim,

yes I am aware of the problem, but I'm still new to mixed-signal so any recommendations on reading are welcome. Thanks a lot!

Aaron

Title: Re: PLL noise contribution
Post by loose-electron on Aug 7^th, 2013, 5:01am

did you do an E2E noise analysis of just the V to I converter and optimize that for noise?

Title: Re: PLL noise contribution
Post by nrk1 on Aug 9^th, 2013, 7:33pm

aaron_do wrote on Jul 23^rd, 2013, 5:56pm:

Hi Tim,

yes I am aware of the problem, but I'm still new to mixed-signal so any recommendations on reading are welcome. Thanks a lot!

Aaron

If power consumption is not an issue, just scale up the V-I converter. By this I mean the part of the circuit that takes the voltage from the loop filter and the bias voltage node that is fed to the current sources in the ring oscillator. You can replicate this by N times to reduce its noise spectral density by N. You can simply connect multiple units in parallel to check this out.

Title: Re: PLL noise contribution
Post by aaron_do on Aug 11^th, 2013, 6:07pm

Hi all,

Quote:

If power consumption is not an issue, just scale up the V-I converter

thanks, but yeah that's the first thing I tried. I found that the current I needed would make the V-I converter more power hungry than the VCO itself. And not only that, the current would have to actually be divided down before the noise from the V-I converter was no longer dominant. I'm now trying out using varactors instead of the fancy V-I converter. It seems the noise is better.

Quote:

did you do an E2E noise analysis of just the V to I converter and optimize that for noise?

well I just looked at the noise summary from the pnoise analysis in spectre and tried to minimize the largest contributors. But I guess its not fool proof because the noise summary seems to plot output noise and not phase noise.

thanks,
Aaron

Title: Re: PLL noise contribution
Post by Ken Kundert on Aug 14^th, 2013, 6:25pm

Quote:

Do you have some reason to believe that the output noise is not dominated by the phase noise? It would be very surprising if the output noise was not dominated by the phase noise for close in noise.

-Ken

Title: Re: PLL noise contribution
Post by aaron_do on Aug 15^th, 2013, 12:11am

Quote:

Do you have some reason to believe that the output noise is not dominated by the phase noise? It would be very surprising if the output noise was not dominated by the phase noise for close in noise.

Actually for some reason I was thinking that the 1 MHz spot noise from the noise summary was literally at 1 MHz instead of 1 MHz from the carrier. But your tip has lead me to a better understanding, so thanks.

Aaron