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Design Languages >> Verilog-AMS >> Verilog-A compiler directive question
https://designers-guide.org/forum/YaBB.pl?num=1374683286

Message started by danmc on Jul 24^th, 2013, 9:28am

Title: Verilog-A compiler directive question
Post by danmc on Jul 24^th, 2013, 9:28am

Is there a way to check multiple macros with an `ifdef? What I would like is:

`define CASE1
// `define CASE2
// `define CASE3

// what I want to do next is
`if defined(CASE1) || defined(CASE2)
// do something
`endif

obviously the defined() bit isn't valid, but is there some easy way of doing this? I suppose I could do:
`ifdef CASE1
`define CASE1_OR_2
`endif

`ifdef CASE2
`define CASE1_OR_2
`endif

`ifdef CASE1_OR_2
//do stuff
`endif

but that seems like an ugly solution. Is there a nicer way?

Thanks
-Dan

Title: Re: Verilog-A compiler directive question
Post by Geoffrey_Coram on Aug 2^nd, 2013, 8:45am

I don't see anything in the LRM that would help; looks like you're stuck with the ugly solution.