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Design >> Mixed-Signal Design >> PLL second order loop filter in practice
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Message started by aaron_do on Jul 25^th, 2013, 11:59pm

Title: PLL second order loop filter in practice
Post by aaron_do on Jul 25^th, 2013, 11:59pm

Hi all,

I have inherited a simple PLL to modify, and it uses a second order loop filter. That is to say 2 capacitors and 1 resistor in the standard placement.

I was reading Dean's Book (just google deansbook4.pdf and its the first link), and on page 178 he calculates values of R1, C1, and C2 based on the users requirements, and also a parameter called "gamma". Later on around page 22 he discusses optimum values of gamma (around 1).

Now for the design I inherited, I found that the value of gamma chosen is around 22. This resulted in the main filter cap (the big one) being around 8x larger than the one calculated from gamma=1.5. Compared to a value of around gamma=1.5, the locking time is significantly worse (maybe 10x), while the phase margin and bandwidth are the same. I have also checked the phase noise for the loop and there's not much difference. It seems like the main effect on the loop was to push the zero to a lower frequency which allows the loop-phase to reach a maximum value of around 70 degrees. For gamma=1.5, the loop-phase reached a maximum of 49 degrees at the unity gain frequency. So the only reason I can think why they would do this is if they are worried about process variation.

Can anybody share some insight into why the previous designer may have done this? Just to give you some example values (i've altered them), here is what I inherited:

Fref = 10 MHz, Fout = 1 GHz, Fcorner = 1 MHz, Phase Margin = 50 degrees, Kvco*Kcp = 2.5p, C2 = 3.92pF, C1 = 154pF, R1 = 32.8 kohm

and here is a more optimum value which I calculated:

Fref = 10 MHz, Fout = 1 GHz, Fcorner = 1 MHz, Phase Margin = 50 degree, Kvco*Kcp = 2.5p, C2 = 2.3 pF, C1 = 15.1 pF, R1 = 29 kohm.

any advice is welcome,

thanks,
Aaron