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Design Languages >> Verilog-AMS >> trouble in simulating verilog-AMS code using Virtuoso ADE
https://designers-guide.org/forum/YaBB.pl?num=1375027498

Message started by susona on Jul 28^th, 2013, 9:04am

Title: trouble in simulating verilog-AMS code using Virtuoso ADE
Post by susona on Jul 28^th, 2013, 9:04am

Hai
i generated verilog code from model writer function in cadence and created symbol for that.

i used this symbol to create the test bench for ADC the problem is in my code i defined output as dout as a 8 bit register but when i created the test bench and netlist it is taking individual bits so i am getting error in simulation can any one help me how to simulate this in virtuoso ADE

Title: Re: trouble in simulating verilog-AMS code using Virtuoso ADE
Post by Geoffrey_Coram on Aug 2^nd, 2013, 8:46am

Does your symbol have a bus pin or individual bit pins?

Title: Re: trouble in simulating verilog-AMS code using Virtuoso ADE
Post by susona on Aug 2^nd, 2013, 9:32am

in my symbol i have only bus pin