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Design >> Mixed-Signal Design >> Mixed-signal decoupling capacitors
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Message started by abcyin_DG on Aug 8^th, 2013, 6:41pm

Title: Mixed-signal decoupling capacitors
Post by abcyin_DG on Aug 8^th, 2013, 6:41pm

Hi, all,

we are designing a mixed signal chip, somebody told me that there should no on-chip decoupling cap for the digital blocks, which should be decoupled with off-chip capacitors, I am wondering that is this true or false?

What is the right way for such mixed signal chip decoupling?

Thanks in advance,
abcyin

Title: Re: Mixed-signal decoupling capacitors
Post by Kevin Aylward on Aug 9^th, 2013, 8:01am

False. Suppose a million gates switch with 1A in 100ps at 10nH of bond inductance? It’s 100V. If there is a lot of digital switching, local, on chip capacitance must be spread throughout the chip. Off chip capacitance for switching spikes, is useless. However… this question leads to sure follow-up advice…make sure you have digital power grounds, analog 0V power rails and analog reference grounds only meeting at ONE star point. It can not be stressed enough that analog 0V for POWERING analog blocks is NOT analog ground. Typically, you will need DIGVSS, ANAVSS, ANAGND, ANAREFGROUND, DIGVDD, ANAVDD, ANAVREF, and more, because there often analog signals that are pure accurate, references, with no or little current in them, and analog signals that have current, but that current should not corrupt other analog reference signals. A mixed signal chip will certainly fail if the power and grounds are not done correctly.