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Design Languages >> Verilog-AMS >> BIAS current modeling in Verilog-a /Verilog-ams
https://designers-guide.org/forum/YaBB.pl?num=1376433256

Message started by hronad on Aug 13^th, 2013, 3:34pm

Title: BIAS current modeling in Verilog-a /Verilog-ams
Post by hronad on Aug 13^th, 2013, 3:34pm

Hi,

I am trying to model a bias current pin (assume 1uA source current), if I define pin as current and assign the value then independent of other block sinking the current, this model will be pumping the current and node voltage can go infinite.

So I defined it as electrical and tried forcing the current and voltage on this pin, then it just takes the voltage assignment, does not show current.

Could you please suggest how to model bias current where if other block not sinking the current, bias pin voltage should go to supply voltage and no current sourcing, as soon as there is sinking model should source constant bias current and voltage on bias pin should drop.

Similarly how to model sink current ? where I check voltage on sink_bias pin, and sink constant current if voltage is above VDS_sat?

Title: Re: BIAS current modeling in Verilog-a /Verilog-ams
Post by boe on Aug 14^th, 2013, 10:06am

hronad wrote on Aug 13^th, 2013, 3:34pm:

Hi,
limit the voltage.
- B O E

Title: Re: BIAS current modeling in Verilog-a /Verilog-ams
Post by Marq Kole on Aug 15^th, 2013, 6:40am

A bit of elaboration - let's assume you're trying to model an NMOS bias current source like the output of a current mirror:
- have the model behave like a current source when the voltage is above a certain threshold (normally close to an NMOS Vth);
- have the model behave like a resistor or an open when the voltage is below that threshold;
- some smoothing between these two regions might improve convergence behavior.

For a PMOS mirror it is obviously the other way around...

Cheers,
Marq