The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> ADC performance impact from narrow band rms jitter on sample CK
https://designers-guide.org/forum/YaBB.pl?num=1378699872

Message started by neoflash on Sep 8^th, 2013, 9:11pm

Title: ADC performance impact from narrow band rms jitter on sample CK
Post by neoflash on Sep 8^th, 2013, 9:11pm

The impact of sample clock jitter on ADC SNR is well described in many papers can be found by google.

However, I never see discussion covering one case that puzzles me:

when the jitter is a narrow band (< 1MHz) gaussian noise and input signal is a sin wave. The ADC output is essentially the PSD of the sampling sin clock with its phase noise.

Since ADC's output is discrete, its PSD is plotted after FFT processing.

My question is: if the FFT bin size is larger or comparable to the bandwidth of phase noise, then all the noise may fall into this signal bin and the result may appear to be jitter free.

Any thoughts? Is my concern valid?

Title: Re: ADC performance impact from narrow band rms jitter on sample CK
Post by aaron_do on Sep 12^th, 2013, 6:10pm

Hi,

I'm no expert in this matter, but I think the signal would just get spread even more. I think you are just convolving your frequency domain signal with the frequency domain version of the windowing function.

regards,
Aaron