The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> PLL measure at divider output
https://designers-guide.org/forum/YaBB.pl?num=1379302336

Message started by aaron_do on Sep 15^th, 2013, 8:32pm

Title: PLL measure at divider output
Post by aaron_do on Sep 15^th, 2013, 8:32pm

Hi all,

I want to try and characterize the jitter and locking time performance of my PLL. I'm wondering is there any issue with measuring the divider output instead of the RF output?

thanks,
Aaron

Title: Re: PLL measure at divider output
Post by raja.cedt on Sep 16^th, 2013, 10:56am

Hello Aaaron,
I don't thing there will be an issue with divider signal monitoring, even if you look into high frequency VCO publication, generally they will integrate the divider and back calculate VCO phase noise. In your case In band PLL noise you have to Multiply N^2 to refer output phase noise. Lock time is similar no need to post-process.

Thanks,
Raj.

Title: Re: PLL measure at divider output
Post by aaron_do on Sep 16^th, 2013, 5:50pm

Great! thanks for the help.

EDIT:

btw, since the phase noise is much lower at 40 MHz, won't that make the accuracy of the measurement worse? For example if I want to measure phase noise, will the noise floor of the spectrum analyzer be a problem? Likewise, for the jitter, the amount of jitter will be a much smaller portion of the total clock period.

Aaron

Title: Re: PLL measure at divider output
Post by tm123 on Sep 17^th, 2013, 11:33am

Aaron,

I agree with Raj that a divider can be used to scale a VCO frequency down to measure its noise. However, remember that the phase noise at the output of the divider will be the following: PN_VCO(dBc/Hz)-10*log(N^2)+PN_DIV(dBc/Hz) where PN_VCO is your VCO output phase noise, N is your divider ratio, and PN_DIV is the output phase noise of the divider itself. For example, if you use a divide by 2, N=2 and the VCO phase noise will be 10*log(4)=6dB lower at the divider output. It is important to note the PN_DIV because that will probably set the phase noise floor at offset frequencies far away from the carrier and you will be measuring the divider phase noise not the VCO phase noise. I think the noise floor of the spectrum analyzer would have the same effect as output phase noise of the divider, it will eventually set the phase noise floor at offset frequencies far from the carrier. Of course, 'far from the carrier' is a relative term based on how good your VCO is and how bad the divider/spectrum analyzer are.

Hope this helps.

Tim

Title: Re: PLL measure at divider output
Post by aaron_do on Sep 17^th, 2013, 6:50pm

Hi Tim,

thanks for the tips. I might not take the divider output after all.

Aaron

Title: Re: PLL measure at divider output
Post by raja.cedt on Oct 8^th, 2013, 3:27am

Dear arron,
Yes you are correct if you divide with larger number then it will any how hit the noise floor, but my assumption in previous post is small divider number. Generally noise floor is will be around -155, so it's hard to hit this floor with -125dB out of band noise. But you are correct if you keep on divide the clock out of band band noise reduction will be off from 6dB, apart from the noise you will have spur aliasing problem also with larger divider number.

Thanks,
Raj.