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Design >> Mixed-Signal Design >> DFF frequency divider minimum frequency of operation
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Message started by aaron_do on Sep 23^rd, 2013, 1:17am

Title: DFF frequency divider minimum frequency of operation
Post by aaron_do on Sep 23^rd, 2013, 1:17am

Hi all,

I have designed a divide by 2 using a single DFF with Qbar fed back to the input, and found that it has a minimum frequency of operation (around 1 MHz). Below the minimum frequency of operation, the output oscillates at the clock rate instead of half the clock rate. Is this typical? The DFF uses dynamic logic. Also, is there a more robust way to design the DFF so that it doesn't face this problem?

Each latch looks something like this:

--------|Clocked INV>---------------|INV>--------------------->
↑ | |
| | |
| | |
CLK |-----<Clocked INV|--------|
↑
|
|
CLKB

thanks,
Aaron

Title: Re: DFF frequency divider minimum frequency of operation
Post by boe on Sep 23^rd, 2013, 3:16am

Hi Aaron,
I would expect dynamic logic to have an f_min. A static FF should not have this problem.
- B O E