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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> how critical is the loop filter capacitor layout in a PLL? https://designers-guide.org/forum/YaBB.pl?num=1380593385 Message started by aaron_do on Sep 30th, 2013, 7:09pm |
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Title: how critical is the loop filter capacitor layout in a PLL? Post by aaron_do on Sep 30th, 2013, 7:09pm Hi all, just wondering how critical is the loop filter capacitor's layout in a PLL? I was thinking to fill up some of my empty space in the layout with the loop filter capacitor. So it would be a little spread out. thanks, Aaron |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by tm123 on Oct 1st, 2013, 11:26am Aaron, The only thing I can think of right now is make sure not to route the VCO control voltage line near anything that could couple to it and cause you spurious headaches. So if one of the plates of the capacitor is connected to the control voltage line make sure you review all other routes around the cap. No signal routing, clock routing, etc. should be near the cap. I will post again if I think of anything else. Tim |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by aaron_do on Oct 1st, 2013, 5:40pm Thanks for the advice. Aaron |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by carlgrace on Dec 25th, 2013, 9:11pm Tim gives good advice. If your PLL depends on an accurate loop filter value it is a poor design. That said, remember that the loop filter control voltage is the holy node for a PLL and needs to be protected at all costs. I would run it from the charge pump to the filter cap on a high metal with a ground shield beneath it. Also, make sure your loop filter cap is shielded and make sure there is a guard ring (preferably double guard rings around it). Remember that the absolute value of on-chip caps can vary by +/- 10 or 15% if you are using MIMs and more than 25% if you are using MOSCAPs. Be sure you can trim your filter caps with register bits. |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by loose-electron on Dec 31st, 2013, 10:58am aaron_do wrote on Sep 30th, 2013, 7:09pm:
Great opportunity to couple noise into the VCO control voltage! If jitter (or phase noise) is not important then go for it. Invariably, the most noise sensitive node in any PLL-VCO is the node between the charge pump out and the VCO in. |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by loose-electron on Dec 31st, 2013, 11:01am carlgrace wrote on Dec 25th, 2013, 9:11pm:
Shield it with a ground where the ground is connected to the VCO reference ground, and only to that ground. - no current in the ground shield - ground on an IC is like a trampoline. |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by aaron_do on Jan 2nd, 2014, 6:34pm Thanks for all the help guys. Quote:
Just wondering, are you implying that the VCO ground should be separate from the rest of the PLL's ground? thanks, Aaron |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by loose-electron on Jan 10th, 2014, 4:29pm aaron_do wrote on Jan 2nd, 2014, 6:34pm:
Impossible to truly separate. You need to process everything differentially and try to optimize your local ground integrity. However, if you are trying to shield a signal, you wish the shield to be referenced to the receiver's ground, and avoid currents in the ground shield. That says the ground shield is connected to the receiver's ground only. |
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Title: Re: how critical is the loop filter capacitor layout in a PLL? Post by aaron_do on Jan 12th, 2014, 4:53pm thanks for the insight Aaron |
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