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Design >> Analog Design >> Opamp Offset for Voltage reference
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Message started by Mikay on Sep 30th, 2013, 7:42pm

Title: Opamp Offset for Voltage reference
Post by Mikay on Sep 30th, 2013, 7:42pm

Here is the issue for my CMOS bulk bandgap. When I change the power supply from 3.2v to 5v. The volatge regerence changes about 6mV. I guess it is due to Opamp offset. When I use another Oapmp. The output show no power supply dependence. Both Opamp has 60dB gain.

Does anybody know Opamp offset is related to the power supply? suppose 1v power supply difference. The systematic offset of the Opamp can vary 1/1000(60dB)~=1mV. The 1mV offset then is amplified by the closed loop and so impact the finial regerence output.

Is my understanding right? if so. How to minimize the systematic offset of the Opamp. Different Opamp has different offset. How much different for different Oapmp. How to choose the right Opamp for Bandgap design.

Thanks for your time.
-Mikay

Title: Re: Opamp Offset for Voltage reference
Post by boe on Oct 1st, 2013, 1:53am


Mikay wrote on Sep 30th, 2013, 7:42pm:
...
Does anybody know Opamp offset is related to the power supply? suppose 1v power supply difference. The systematic offset of the Opamp can vary 1/1000(60dB)~=1mV. The 1mV offset then is amplified by the closed loop and so impact the finial regerence output.

Is my understanding right? ...
No. You want to look for the PSRR.

Title: Re: Opamp Offset for Voltage reference
Post by raja.cedt on Oct 1st, 2013, 5:21am

I guess it is not only because of opamp, just to confirm replace op amp with ideal VCVS and run the sim, if you don't get any dependency then opamp is the culprit, But many times it is because of BGR pmos gds change also (again it depends on the architecture)

Title: Re: Opamp Offset for Voltage reference
Post by avlsi on Oct 1st, 2013, 6:31am

Changing the power supply might have changed the VDS across current sources, resulting in increasing or decreasing current and there by changing your reference voltage!!

Title: Re: Opamp Offset for Voltage reference
Post by Mikay on Oct 1st, 2013, 7:07pm

The Opamp has to supply much current to the bandgap. One of the Opamp gain decrease too much when source 200uA current to BGR. So the loop gain deteriates... It's PSR issue.I adopt a class AB Opamp to drive BGR. Then PSR becomes good. Thanks for your hint.
boe wrote on Oct 1st, 2013, 1:53am:

Mikay wrote on Sep 30th, 2013, 7:42pm:
...
Does anybody know Opamp offset is related to the power supply? suppose 1v power supply difference. The systematic offset of the Opamp can vary 1/1000(60dB)~=1mV. The 1mV offset then is amplified by the closed loop and so impact the finial regerence output.

Is my understanding right? ...
No. You want to look for the PSRR.


Title: Re: Opamp Offset for Voltage reference
Post by Mikay on Oct 1st, 2013, 7:10pm

Thanks raja. My Opamp directly drive the PNP and resistor and feed current to them.
raja.cedt wrote on Oct 1st, 2013, 5:21am:
I guess it is not only because of opamp, just to confirm replace op amp with ideal VCVS and run the sim, if you don't get any dependency then opamp is the culprit, But many times it is because of BGR pmos gds change also (again it depends on the architecture)


Title: Re: Opamp Offset for Voltage reference
Post by Mikay on Oct 1st, 2013, 7:15pm

Yes avlsi and this is usually also the path introducing PSR issue!
avlsi wrote on Oct 1st, 2013, 6:31am:
Changing the power supply might have changed the VDS across current sources, resulting in increasing or decreasing current and there by changing your reference voltage!!


Title: Re: Opamp Offset for Voltage reference
Post by Larry_80 on Oct 12th, 2013, 9:01pm

Why dont you cascode your PMOS...like some suggesed, your PMOS current source seems sensitive to VDS......so a good way to mediate that is to add another PMOS stack.

Title: Re: Opamp Offset for Voltage reference
Post by Mikay on Oct 14th, 2013, 7:57pm

These PMOS slow down the settling time while I need a pretty fast start-up.
Larry_80 wrote on Oct 12th, 2013, 9:01pm:
Why dont you cascode your PMOS...like some suggesed, your PMOS current source seems sensitive to VDS......so a good way to mediate that is to add another PMOS stack.


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