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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Why are ro1 and ro2 modeled in parallel here? https://designers-guide.org/forum/YaBB.pl?num=1381051701 Message started by baab on Oct 6th, 2013, 2:28am |
Title: Why are ro1 and ro2 modeled in parallel here? Post by baab on Oct 6th, 2013, 2:28am Hi, I am reading about Noise in Design of Analog CMOS Integrated Circuits Behzad Razavi. Please help me with this question. Thank you. |
Title: Re: Why are ro1 and ro2 modeled in parallel here? Post by raja.cedt on Oct 6th, 2013, 4:06am Correct... To calculate noise 1. Drwa small signal picture 2. Add one transistor noise (could be current or voltage) 3. Find the output voltage/current. Thanks, Raj. |
Title: Re: Why are ro1 and ro2 modeled in parallel here? Post by baab on Oct 6th, 2013, 4:50am Thank you for the confirmation. |
Title: Re: Why are ro1 and ro2 modeled in parallel here? Post by aaron_do on Oct 7th, 2013, 5:51pm Hi baab, Quote:
the transistors don't need to be operating in saturation for the noise to be considered small. Noise is usually a small signal. If it wasn't then you would have a tough time detecting your signal inside the noise... regards, Aaron |
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