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Design >> Mixed-Signal Design >> Modeling Jitter in PLL-based Frequency Synthesizers
https://designers-guide.org/forum/YaBB.pl?num=1381828650

Message started by mustangyhz on Oct 15^th, 2013, 2:17am

Title: Modeling Jitter in PLL-based Frequency Synthesizers
Post by mustangyhz on Oct 15^th, 2013, 2:17am

Does anybody download "Modeling Jitter in PLL-based Frequency Synthesizers" from www.designers-guide.org and test it in cadence?
How to simulate it? can you send me the project in cadence? thanks!