The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> Sample and hold clock bootstrap
https://designers-guide.org/forum/YaBB.pl?num=1381915238

Message started by aaron_do on Oct 16^th, 2013, 2:20am

Title: Sample and hold clock bootstrap
Post by aaron_do on Oct 16^th, 2013, 2:20am

Hi all,

for a medium speed high resolution ADC, around 200 MSamples/s and 14-bit, do we normally bootstrap the sample and hold switch, or should I just oversize the sampling switch so that it can settle sufficiently under all conditions? Also, does anybody know any good references for bootstrapping the switch?

thanks,
Aaron

Title: Re: Sample and hold clock bootstrap
Post by raja.cedt on Oct 16^th, 2013, 2:48am

I am not an expert in this field, but with over sizing the switch you will reduce the R but you will not solve signal dependent resister which impact linearity.

Please have a look on this video, well treatment!!!

http://nptel.iitm.ac.in/courses/117106034/7
http://nptel.iitm.ac.in/courses/117106034/8

Thanks,
Raj.

Title: Re: Sample and hold clock bootstrap
Post by aaron_do on Oct 16^th, 2013, 5:43pm

Hi Raj.,

thanks. I will check out the videos when I can. I figured that if my switch is big enough, then the linearity will not be an issue. For instance, as long as it settles to less than LSB/2, then any nonlinearity will be indistinguishable from the quantization noise. I believe it will add to the quantization noise, but again, if its small enough, there won't be much impact.

Anyway it seems you're saying bootstrapping is a good idea.

thanks,
Aaron

Title: Re: Sample and hold clock bootstrap
Post by Lazarus on Oct 17^th, 2013, 10:26am

Aaron,

Whether a switch is sufficient on its own or not depends on the input common mode and swing (depending on the CM, you'd use NMOS, PMOS, or CMOS).

However, if your swing is large enough, simply sizing up your switch won't be enough for 14+bits and for moderate input frequencies, because the transistor capacitance also increases. Hence, eventually, your RC delay (which is what matters) converges to a constant.

Bootstrapping is an easy solution to all this.

-- L

Title: Re: Sample and hold clock bootstrap
Post by aaron_do on Oct 17^th, 2013, 6:24pm

Hi Lazarus,

thanks for the reply. Actually another problem associated with the large switch is the charge injection. Bootstrapping made the charge injection more linear, but I am still having a lot of trouble meeting requirements even in simulation.

I am simulating a simple sample and hold with bootstrapping, and I find the droop due to charge injection to have a variation of around 0.5 mV across the input swing. For a full scale of 1 V, that amounts to just 11 bits of resolution 1 LSB. Any clues as to how this problem is normally tackled? I understand I can try bottom plate sampling, or using a dummy transistor. Just wondering what is normally done.

thanks,
Aaron

Title: Re: Sample and hold clock bootstrap
Post by Lazarus on Oct 18^th, 2013, 6:23am

Aaron,

OK, I had assumed you were bottom-plate sampling.

Here are several things you will need to check:

1 - If you decrease the sample rate (for the same input frequency), does the performance improve? If it does, then this tells you that the bootstrap circuit is taking time to charge up (and cutting down the track time).
2 - If you decrease the input frequency for the same sample frequency, does the performance improve? If it does, then one possible reason is the phase delay of the bootstrapped signal at the gate as compared to the source / drain.
3 - How much does the bootstrapped voltage drop when the TH goes from hold to track (due to the parasitic caps)?

Finally, note that the on resistance is inversely proportional to VGS-VT. Bootstrapping holds VGS constant. VT is still nonlinear. If you can control the body in your process, then you will need to make VSB = 0 during track mode.

By the way, dummy transistors won't work for the linearity you are targeting.

-- L

Title: Re: Sample and hold clock bootstrap
Post by aaron_do on Oct 18^th, 2013, 6:50am

Hi Lazarus,

thanks for all the useful pointers. I'll have a look into them next week. I have started looking into other methods such as bottom-plate sampling and series sampling too.

Decreasing the input frequency only improved the situation marginally. I haven't tried reducing the sampling frequency (that will have to wait until next week), but the clock does appear to be well settled.

thanks,
Aaron